diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
index 4db620c..233a6de 100644
--- a/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
+++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
@@ -48,9 +48,6 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
   ER_ROM1 __ROM1_BASE __ROM1_SIZE {
     *(+RO +XO)
   }
-}
-
-LR_RAM0 __RAM0_BASE NOCOMPRESS {
 
   RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
     *.o(.bss.noinit)
diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src b/board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src
new file mode 100644
index 0000000..545300e
--- /dev/null
+++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src
@@ -0,0 +1,386 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright © 2019 Keith Packard
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx!w)  : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
+#if __ROM1_SIZE > 0
+  ROM1  (rx!w)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx!w)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx!w)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
+#if __RAM1_SIZE > 0
+  RAM1  (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+ENTRY(Reset_Handler)
+
+PHDRS
+{
+    boot PT_LOAD;
+    text PT_LOAD;
+    ram PT_LOAD;
+    ram_init PT_LOAD;
+    tls PT_TLS;
+}
+
+SECTIONS
+{
+    .init : {
+        KEEP (*(.vectors))
+
+        /* Disable by default
+         *
+         * *.init.enter contains a vector table provided by picolibc,
+         * whereas CMSIS already provides a vector table via .vectors
+         */
+        /*
+        KEEP (*(.text.init.enter))
+        KEEP (*(.data.init.enter))
+        */
+
+        KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*)))
+    } >ROM0 AT>ROM0 :boot
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    .veneers :
+    {
+        . = ALIGN(32);
+        KEEP(*(.gnu.sgstubs))
+    } > ROM0 AT>ROM0 :boot
+#endif
+
+    .text : {
+
+        /* code */
+        *(.text.unlikely .text.unlikely.*)
+        *(.text.startup .text.startup.*)
+        *(.text .text.* .opd .opd.*)
+        *(.gnu.linkonce.t.*)
+        KEEP (*(.fini .fini.*))
+        __text_end = .;
+
+        PROVIDE (__etext = __text_end);
+        PROVIDE (_etext = __text_end);
+        PROVIDE (etext = __text_end);
+
+        /* read-only data */
+        *(.rdata)
+        *(.rodata .rodata.*)
+        *(.gnu.linkonce.r.*)
+
+        *(.srodata.cst16)
+        *(.srodata.cst8)
+        *(.srodata.cst4)
+        *(.srodata.cst2)
+        *(.srodata .srodata.*)
+        *(.data.rel.ro .data.rel.ro.*)
+        *(.got .got.*)
+
+        /* Need to pre-align so that the symbols come after padding */
+        . = ALIGN(8);
+
+        /* lists of constructors and destructors */
+        PROVIDE_HIDDEN ( __bothinit_array_start = . );
+        PROVIDE_HIDDEN ( __preinit_array_start = . );
+        KEEP (*(.preinit_array))
+        PROVIDE_HIDDEN ( __preinit_array_end = . );
+
+        PROVIDE_HIDDEN ( __init_array_start = . );
+        KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+        KEEP (*(.init_array .ctors))
+        PROVIDE_HIDDEN ( __init_array_end = . );
+        PROVIDE_HIDDEN ( __bothinit_array_end = . );
+
+        PROVIDE_HIDDEN ( __fini_array_start = . );
+        KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+        KEEP (*(.fini_array .dtors))
+        PROVIDE_HIDDEN ( __fini_array_end = . );
+
+    } >ROM1 AT>ROM1 :text
+
+    .toc : {
+        *(.toc .toc.*)
+    } >ROM1 AT>ROM1 :text
+
+    /* additional sections when compiling with C++ exception support */
+
+    .except_ordered : {
+        *(.gcc_except_table *.gcc_except_table.*)
+        KEEP (*(.eh_frame .eh_frame.*))
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } >ROM1 AT>ROM1 :text
+
+    .except_unordered : {
+        . = ALIGN(8);
+
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx*)
+        PROVIDE(__exidx_end = .);
+    } >ROM1 AT>ROM1 :text
+
+
+    /*
+     * Data values which are preserved across reset
+     */
+    .preserve (NOLOAD) : {
+        PROVIDE(__preserve_start__ = .);
+        KEEP(*(SORT_BY_NAME(.preserve.*)))
+        KEEP(*(.preserve))
+        PROVIDE(__preserve_end__ = .);
+    } >RAM0 AT>RAM0 :ram
+
+    .data :  {
+        *(.data .data.*)
+        *(.gnu.linkonce.d.*)
+
+        /* Need to pre-align so that the symbols come after padding */
+        . = ALIGN(8);
+
+        PROVIDE( __global_pointer$ = . + 0x800 );
+        *(.sdata .sdata.* .sdata2.*)
+        *(.gnu.linkonce.s.*)
+    } >RAM0 AT>ROM1 :ram_init
+    PROVIDE(__data_start = ADDR(.data));
+    PROVIDE(__data_source = LOADADDR(.data));
+
+    /* Thread local initialized data. This gets
+     * space allocated as it is expected to be placed
+     * in ram to be used as a template for TLS data blocks
+     * allocated at runtime. We're slightly abusing that
+     * by placing the data in flash where it will be copied
+     * into the allocate ram addresses by the existing
+     * data initialization code in crt0
+     */
+    .tdata :  {
+        *(.tdata .tdata.* .gnu.linkonce.td.*)
+        PROVIDE(__data_end = .);
+        PROVIDE(__tdata_end = .);
+    } >RAM0 AT>ROM1 :tls :ram_init
+    PROVIDE( __tls_base = ADDR(.tdata));
+    PROVIDE( __tdata_start = ADDR(.tdata));
+    PROVIDE( __tdata_source = LOADADDR(.tdata) );
+    PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) );
+    PROVIDE( __data_source_end = __tdata_source_end );
+    PROVIDE( __tdata_size = SIZEOF(.tdata) );
+    PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) );
+
+    PROVIDE( __edata = __data_end );
+    PROVIDE( _edata = __data_end );
+    PROVIDE( edata = __data_end );
+    PROVIDE( __data_size = __data_end - __data_start );
+    PROVIDE( __data_source_size = __data_source_end - __data_source );
+
+    .tbss (NOLOAD) : {
+        *(.tbss .tbss.* .gnu.linkonce.tb.*)
+        *(.tcommon)
+        PROVIDE( __tls_end = . );
+        PROVIDE( __tbss_end = . );
+    } >RAM0 AT>RAM0 :tls :ram
+    PROVIDE( __bss_start = ADDR(.tbss));
+    PROVIDE( __tbss_start = ADDR(.tbss));
+    PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) );
+    PROVIDE( __tbss_size = SIZEOF(.tbss) );
+    PROVIDE( __tls_size = __tls_end - __tls_base );
+    PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );
+    PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );
+    PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) );
+
+    /*
+     * The linker special cases .tbss segments which are
+     * identified as segments which are not loaded and are
+     * thread_local.
+     *
+     * For these segments, the linker does not advance 'dot'
+     * across them.  We actually need memory allocated for tbss,
+     * so we create a special segment here just to make room
+     */
+    /*
+    .tbss_space (NOLOAD) : {
+        . = ADDR(.tbss);
+        . = . + SIZEOF(.tbss);
+    } >RAM0 AT>RAM0 :ram
+    */
+
+    .bss (NOLOAD) : {
+        *(.sbss*)
+        *(.gnu.linkonce.sb.*)
+        *(.bss .bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+
+        /* Align the end of this section, so next can start on aligned address */
+        . = ALIGN(8);
+        __bss_end = .;
+    } >RAM0 AT>RAM0 :ram
+    PROVIDE( __non_tls_bss_start = ADDR(.bss) );
+    PROVIDE( __bss_size = __bss_end - __bss_start );
+
+    /* This section contains data that is not initialized during load,
+       or during the application's initialization sequence. */
+    .noinit (NOLOAD) : {
+        __noinit_start__ = .;
+        *(.noinit)
+        *(.noinit.*)
+
+        /* Align the end of this section, so next (heap) can start on aligned address */
+        . = ALIGN(8);
+        __noinit_end__ = .;
+    } >RAM0 AT>RAM0 :ram
+
+    PROVIDE( __end = . );
+    PROVIDE( _end = . );
+    PROVIDE( end = . );
+
+    /* Make the rest of memory available for heap storage */
+    PROVIDE (__heap_start = __end);
+#ifdef __HEAP_SIZE
+    PROVIDE (__heap_end = __heap_start + __HEAP_SIZE);
+    PROVIDE (__heap_size = __HEAP_SIZE);
+#else
+    PROVIDE (__heap_end = __stack - __STACK_SIZE);
+    PROVIDE (__heap_size = __heap_end - __heap_start);
+#endif
+    .heap (NOLOAD) : {
+        . += __heap_size;
+    } >RAM0 :ram
+
+    /* Define a stack region to make sure it fits in memory */
+    PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE);
+    PROVIDE(__stack_limit = __stack - __STACK_SIZE);
+    .stack (__stack_limit) (NOLOAD) : {
+        . += __STACK_SIZE;
+    } >RAM0 :ram
+
+#if __STACKSEAL_SIZE > 0
+    PROVIDE(__stack_seal = __stack);
+    .stackseal (__stack) (NOLOAD) :
+    {
+        . += __STACKSEAL_SIZE;
+    } >RAM0 :ram
+#endif
+
+    /* Throw away C++ exception handling information */
+
+    /*
+
+    /DISCARD/ : {
+        *(.note .note.*)
+        *(.eh_frame .eh_frame.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.ARM.exidx*)
+    }
+
+    */
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
+    /* DWARF debug sections.
+       Symbols in the DWARF debugging sections are relative to the beginning
+       of the section so we begin them at 0.  */
+    /* DWARF 1.  */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions.  */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2.  */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2.  */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions.  */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+    /* DWARF 3.  */
+    .debug_pubtypes 0 : { *(.debug_pubtypes) }
+    .debug_ranges   0 : { *(.debug_ranges) }
+    /* DWARF 5.  */
+    .debug_addr     0 : { *(.debug_addr) }
+    .debug_line_str 0 : { *(.debug_line_str) }
+    .debug_loclists 0 : { *(.debug_loclists) }
+    .debug_macro    0 : { *(.debug_macro) }
+    .debug_names    0 : { *(.debug_names) }
+    .debug_rnglists 0 : { *(.debug_rnglists) }
+    .debug_str_offsets 0 : { *(.debug_str_offsets) }
+    .debug_sup      0 : { *(.debug_sup) }
+    .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+}
+/*
+ * Check that sections that are copied from flash to RAM have matching
+ * padding, so that a single memcpy() of __data_size copies the correct bytes.
+ */
+ASSERT( __data_size == __data_source_size,
+    "ERROR: .data/.tdata flash size does not match RAM size");
diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src b/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src
index ea02d53..1a3548b 100644
--- a/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src
+++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src
@@ -42,8 +42,6 @@ define memory mem with size = 4G;
   define region ROM3_region = [];
 #endif
 
-define region ROM_region = ROM0_region |  ROM1_region | ROM2_region | ROM3_region;
-
 #if __RAM0_SIZE > 0
   define region RAM0_region = mem:[from __RAM0_BASE to (__RAM0_BASE+__RAM0_SIZE-1)];
 #else
@@ -68,8 +66,6 @@ define region ROM_region = ROM0_region |  ROM1_region | ROM2_region | ROM3_regio
   define region RAM3_region = [];
 #endif
 
-define region RAM_region = RAM0_region | RAM1_region | RAM2_region | RAM3_region;
-
 do not initialize  { section .noinit };
 initialize by copy { readwrite };
 if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
@@ -80,15 +76,16 @@ if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
 
 place at address mem:__ROM0_BASE { readonly section .intvec };
 
-if (!isempty(ROM_region))
+if (!isempty(ROM1_region))
 {
-  place in ROM_region  { readonly };
+  place in ROM1_region { readonly };
 }
 
-if (!isempty(RAM_region))
+if (!isempty(RAM0_region))
 {
   define block CSTACK     with alignment = 8, size = __STACK_SIZE     { };
   define block PROC_STACK with alignment = 8, size = 0 { };
   define block HEAP       with alignment = 8, size = __HEAP_SIZE       { };
-  place in RAM_region  { readwrite, block CSTACK, block PROC_STACK, block HEAP };
+  place in RAM0_region { readwrite, block PROC_STACK, block HEAP };
+  place at end of RAM0_region { block CSTACK };
 }
diff --git a/board/Corstone-300/sse300_memmap_ns.h b/board/Corstone-300/sse300_memmap_ns.h
index d15a465..811a1c6 100644
--- a/board/Corstone-300/sse300_memmap_ns.h
+++ b/board/Corstone-300/sse300_memmap_ns.h
@@ -57,10 +57,10 @@
 #define SRAM_VM1_NS_LIMIT               (SRAM_VM1_NS_BASE + SRAM_VM1_NS_SIZE - 1)
 
 /*---------------------------------------------------------------------------*/
-/*                         Secure QSPI Flash Regions                         */
+/*                         Non-Secure QSPI Flash Regions                     */
 /*---------------------------------------------------------------------------*/
 
-/* QSPI Flash - Secure */
+/* QSPI Flash - Non-Secure */
 #define QSPI_FLASH_NS_BASE              0x28000000
 #define QSPI_FLASH_NS_SIZE              0x00800000    /* 8MB */
 #define QSPI_FLASH_NS_LIMIT             (QSPI_FLASH_NS_BASE + QSPI_FLASH_NS_SIZE - 1)
diff --git a/board/Corstone-310/sse310_memmap_ns.h b/board/Corstone-310/sse310_memmap_ns.h
index af37d33..ac33d65 100644
--- a/board/Corstone-310/sse310_memmap_ns.h
+++ b/board/Corstone-310/sse310_memmap_ns.h
@@ -57,10 +57,10 @@
 #define SRAM_VM1_NS_LIMIT               (SRAM_VM1_NS_BASE + SRAM_VM1_NS_SIZE - 1)
 
 /*---------------------------------------------------------------------------*/
-/*                         Secure QSPI Flash Regions                         */
+/*                         Non-Secure QSPI Flash Regions                     */
 /*---------------------------------------------------------------------------*/
 
-/* QSPI Flash - Secure */
+/* QSPI Flash - Non-Secure */
 #define QSPI_FLASH_NS_BASE              0x28000000
 #define QSPI_FLASH_NS_SIZE              0x00800000    /* 8MB */
 #define QSPI_FLASH_NS_LIMIT             (QSPI_FLASH_NS_BASE + QSPI_FLASH_NS_SIZE - 1)
diff --git a/board/Corstone-315/sse315_memmap_ns.h b/board/Corstone-315/sse315_memmap_ns.h
index 354f78b..0bfb56b 100644
--- a/board/Corstone-315/sse315_memmap_ns.h
+++ b/board/Corstone-315/sse315_memmap_ns.h
@@ -16,8 +16,8 @@
  * limitations under the License.
  *---------------------------------------------------------------------------*/
 
-#ifndef SSE320_MEMMAP_NS_H
-#define SSE320_MEMMAP_NS_H
+#ifndef SSE315_MEMMAP_NS_H
+#define SSE315_MEMMAP_NS_H
 
 /*============================================================================*/
 /*                           NON-SECURE MEMORY REGIONS                        */
@@ -99,4 +99,4 @@
 #define DDR4_6_NS_SIZE                  0x10000000    /* 256MB */
 #define DDR4_6_NS_LIMIT                 (DDR4_6_NS_BASE + DDR4_6_NS_SIZE - 1)
 
-#endif /* SSE320_MEMMAP_NS_H */
+#endif /* SSE315_MEMMAP_NS_H */
diff --git a/board/Corstone-315/sse315_memmap_s.h b/board/Corstone-315/sse315_memmap_s.h
index 42d7691..2d43b97 100644
--- a/board/Corstone-315/sse315_memmap_s.h
+++ b/board/Corstone-315/sse315_memmap_s.h
@@ -16,8 +16,8 @@
  * limitations under the License.
  *---------------------------------------------------------------------------*/
 
-#ifndef SSE320_MEMMAP_S_H
-#define SSE320_MEMMAP_S_H
+#ifndef SSE315_MEMMAP_S_H
+#define SSE315_MEMMAP_S_H
 
 /*============================================================================*/
 /*                             SECURE MEMORY REGIONS                          */
@@ -104,4 +104,4 @@
 #define DDR4_7_S_SIZE                   0x10000000    /* 256MB */
 #define DDR4_7_S_LIMIT                  (DDR4_7_S_BASE + DDR4_7_S_SIZE - 1)
 
-#endif /* SSE320_MEMMAP_S_H */
+#endif /* SSE315_MEMMAP_S_H */
diff --git a/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
index 4db620c..233a6de 100644
--- a/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
+++ b/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
@@ -48,9 +48,6 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
   ER_ROM1 __ROM1_BASE __ROM1_SIZE {
     *(+RO +XO)
   }
-}
-
-LR_RAM0 __RAM0_BASE NOCOMPRESS {
 
   RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
     *.o(.bss.noinit)
diff --git a/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src b/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src
new file mode 100644
index 0000000..545300e
--- /dev/null
+++ b/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src
@@ -0,0 +1,386 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright © 2019 Keith Packard
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx!w)  : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
+#if __ROM1_SIZE > 0
+  ROM1  (rx!w)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx!w)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx!w)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
+#if __RAM1_SIZE > 0
+  RAM1  (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+ENTRY(Reset_Handler)
+
+PHDRS
+{
+    boot PT_LOAD;
+    text PT_LOAD;
+    ram PT_LOAD;
+    ram_init PT_LOAD;
+    tls PT_TLS;
+}
+
+SECTIONS
+{
+    .init : {
+        KEEP (*(.vectors))
+
+        /* Disable by default
+         *
+         * *.init.enter contains a vector table provided by picolibc,
+         * whereas CMSIS already provides a vector table via .vectors
+         */
+        /*
+        KEEP (*(.text.init.enter))
+        KEEP (*(.data.init.enter))
+        */
+
+        KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*)))
+    } >ROM0 AT>ROM0 :boot
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    .veneers :
+    {
+        . = ALIGN(32);
+        KEEP(*(.gnu.sgstubs))
+    } > ROM0 AT>ROM0 :boot
+#endif
+
+    .text : {
+
+        /* code */
+        *(.text.unlikely .text.unlikely.*)
+        *(.text.startup .text.startup.*)
+        *(.text .text.* .opd .opd.*)
+        *(.gnu.linkonce.t.*)
+        KEEP (*(.fini .fini.*))
+        __text_end = .;
+
+        PROVIDE (__etext = __text_end);
+        PROVIDE (_etext = __text_end);
+        PROVIDE (etext = __text_end);
+
+        /* read-only data */
+        *(.rdata)
+        *(.rodata .rodata.*)
+        *(.gnu.linkonce.r.*)
+
+        *(.srodata.cst16)
+        *(.srodata.cst8)
+        *(.srodata.cst4)
+        *(.srodata.cst2)
+        *(.srodata .srodata.*)
+        *(.data.rel.ro .data.rel.ro.*)
+        *(.got .got.*)
+
+        /* Need to pre-align so that the symbols come after padding */
+        . = ALIGN(8);
+
+        /* lists of constructors and destructors */
+        PROVIDE_HIDDEN ( __bothinit_array_start = . );
+        PROVIDE_HIDDEN ( __preinit_array_start = . );
+        KEEP (*(.preinit_array))
+        PROVIDE_HIDDEN ( __preinit_array_end = . );
+
+        PROVIDE_HIDDEN ( __init_array_start = . );
+        KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+        KEEP (*(.init_array .ctors))
+        PROVIDE_HIDDEN ( __init_array_end = . );
+        PROVIDE_HIDDEN ( __bothinit_array_end = . );
+
+        PROVIDE_HIDDEN ( __fini_array_start = . );
+        KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+        KEEP (*(.fini_array .dtors))
+        PROVIDE_HIDDEN ( __fini_array_end = . );
+
+    } >ROM1 AT>ROM1 :text
+
+    .toc : {
+        *(.toc .toc.*)
+    } >ROM1 AT>ROM1 :text
+
+    /* additional sections when compiling with C++ exception support */
+
+    .except_ordered : {
+        *(.gcc_except_table *.gcc_except_table.*)
+        KEEP (*(.eh_frame .eh_frame.*))
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } >ROM1 AT>ROM1 :text
+
+    .except_unordered : {
+        . = ALIGN(8);
+
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx*)
+        PROVIDE(__exidx_end = .);
+    } >ROM1 AT>ROM1 :text
+
+
+    /*
+     * Data values which are preserved across reset
+     */
+    .preserve (NOLOAD) : {
+        PROVIDE(__preserve_start__ = .);
+        KEEP(*(SORT_BY_NAME(.preserve.*)))
+        KEEP(*(.preserve))
+        PROVIDE(__preserve_end__ = .);
+    } >RAM0 AT>RAM0 :ram
+
+    .data :  {
+        *(.data .data.*)
+        *(.gnu.linkonce.d.*)
+
+        /* Need to pre-align so that the symbols come after padding */
+        . = ALIGN(8);
+
+        PROVIDE( __global_pointer$ = . + 0x800 );
+        *(.sdata .sdata.* .sdata2.*)
+        *(.gnu.linkonce.s.*)
+    } >RAM0 AT>ROM1 :ram_init
+    PROVIDE(__data_start = ADDR(.data));
+    PROVIDE(__data_source = LOADADDR(.data));
+
+    /* Thread local initialized data. This gets
+     * space allocated as it is expected to be placed
+     * in ram to be used as a template for TLS data blocks
+     * allocated at runtime. We're slightly abusing that
+     * by placing the data in flash where it will be copied
+     * into the allocate ram addresses by the existing
+     * data initialization code in crt0
+     */
+    .tdata :  {
+        *(.tdata .tdata.* .gnu.linkonce.td.*)
+        PROVIDE(__data_end = .);
+        PROVIDE(__tdata_end = .);
+    } >RAM0 AT>ROM1 :tls :ram_init
+    PROVIDE( __tls_base = ADDR(.tdata));
+    PROVIDE( __tdata_start = ADDR(.tdata));
+    PROVIDE( __tdata_source = LOADADDR(.tdata) );
+    PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) );
+    PROVIDE( __data_source_end = __tdata_source_end );
+    PROVIDE( __tdata_size = SIZEOF(.tdata) );
+    PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) );
+
+    PROVIDE( __edata = __data_end );
+    PROVIDE( _edata = __data_end );
+    PROVIDE( edata = __data_end );
+    PROVIDE( __data_size = __data_end - __data_start );
+    PROVIDE( __data_source_size = __data_source_end - __data_source );
+
+    .tbss (NOLOAD) : {
+        *(.tbss .tbss.* .gnu.linkonce.tb.*)
+        *(.tcommon)
+        PROVIDE( __tls_end = . );
+        PROVIDE( __tbss_end = . );
+    } >RAM0 AT>RAM0 :tls :ram
+    PROVIDE( __bss_start = ADDR(.tbss));
+    PROVIDE( __tbss_start = ADDR(.tbss));
+    PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) );
+    PROVIDE( __tbss_size = SIZEOF(.tbss) );
+    PROVIDE( __tls_size = __tls_end - __tls_base );
+    PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );
+    PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );
+    PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) );
+
+    /*
+     * The linker special cases .tbss segments which are
+     * identified as segments which are not loaded and are
+     * thread_local.
+     *
+     * For these segments, the linker does not advance 'dot'
+     * across them.  We actually need memory allocated for tbss,
+     * so we create a special segment here just to make room
+     */
+    /*
+    .tbss_space (NOLOAD) : {
+        . = ADDR(.tbss);
+        . = . + SIZEOF(.tbss);
+    } >RAM0 AT>RAM0 :ram
+    */
+
+    .bss (NOLOAD) : {
+        *(.sbss*)
+        *(.gnu.linkonce.sb.*)
+        *(.bss .bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+
+        /* Align the end of this section, so next can start on aligned address */
+        . = ALIGN(8);
+        __bss_end = .;
+    } >RAM0 AT>RAM0 :ram
+    PROVIDE( __non_tls_bss_start = ADDR(.bss) );
+    PROVIDE( __bss_size = __bss_end - __bss_start );
+
+    /* This section contains data that is not initialized during load,
+       or during the application's initialization sequence. */
+    .noinit (NOLOAD) : {
+        __noinit_start__ = .;
+        *(.noinit)
+        *(.noinit.*)
+
+        /* Align the end of this section, so next (heap) can start on aligned address */
+        . = ALIGN(8);
+        __noinit_end__ = .;
+    } >RAM0 AT>RAM0 :ram
+
+    PROVIDE( __end = . );
+    PROVIDE( _end = . );
+    PROVIDE( end = . );
+
+    /* Make the rest of memory available for heap storage */
+    PROVIDE (__heap_start = __end);
+#ifdef __HEAP_SIZE
+    PROVIDE (__heap_end = __heap_start + __HEAP_SIZE);
+    PROVIDE (__heap_size = __HEAP_SIZE);
+#else
+    PROVIDE (__heap_end = __stack - __STACK_SIZE);
+    PROVIDE (__heap_size = __heap_end - __heap_start);
+#endif
+    .heap (NOLOAD) : {
+        . += __heap_size;
+    } >RAM0 :ram
+
+    /* Define a stack region to make sure it fits in memory */
+    PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE);
+    PROVIDE(__stack_limit = __stack - __STACK_SIZE);
+    .stack (__stack_limit) (NOLOAD) : {
+        . += __STACK_SIZE;
+    } >RAM0 :ram
+
+#if __STACKSEAL_SIZE > 0
+    PROVIDE(__stack_seal = __stack);
+    .stackseal (__stack) (NOLOAD) :
+    {
+        . += __STACKSEAL_SIZE;
+    } >RAM0 :ram
+#endif
+
+    /* Throw away C++ exception handling information */
+
+    /*
+
+    /DISCARD/ : {
+        *(.note .note.*)
+        *(.eh_frame .eh_frame.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.ARM.exidx*)
+    }
+
+    */
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
+    /* DWARF debug sections.
+       Symbols in the DWARF debugging sections are relative to the beginning
+       of the section so we begin them at 0.  */
+    /* DWARF 1.  */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions.  */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2.  */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2.  */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions.  */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+    /* DWARF 3.  */
+    .debug_pubtypes 0 : { *(.debug_pubtypes) }
+    .debug_ranges   0 : { *(.debug_ranges) }
+    /* DWARF 5.  */
+    .debug_addr     0 : { *(.debug_addr) }
+    .debug_line_str 0 : { *(.debug_line_str) }
+    .debug_loclists 0 : { *(.debug_loclists) }
+    .debug_macro    0 : { *(.debug_macro) }
+    .debug_names    0 : { *(.debug_names) }
+    .debug_rnglists 0 : { *(.debug_rnglists) }
+    .debug_str_offsets 0 : { *(.debug_str_offsets) }
+    .debug_sup      0 : { *(.debug_sup) }
+    .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+}
+/*
+ * Check that sections that are copied from flash to RAM have matching
+ * padding, so that a single memcpy() of __data_size copies the correct bytes.
+ */
+ASSERT( __data_size == __data_source_size,
+    "ERROR: .data/.tdata flash size does not match RAM size");
diff --git a/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src b/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src
index ea02d53..1a3548b 100644
--- a/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src
+++ b/example/FVP_Audio/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src
@@ -42,8 +42,6 @@ define memory mem with size = 4G;
   define region ROM3_region = [];
 #endif
 
-define region ROM_region = ROM0_region |  ROM1_region | ROM2_region | ROM3_region;
-
 #if __RAM0_SIZE > 0
   define region RAM0_region = mem:[from __RAM0_BASE to (__RAM0_BASE+__RAM0_SIZE-1)];
 #else
@@ -68,8 +66,6 @@ define region ROM_region = ROM0_region |  ROM1_region | ROM2_region | ROM3_regio
   define region RAM3_region = [];
 #endif
 
-define region RAM_region = RAM0_region | RAM1_region | RAM2_region | RAM3_region;
-
 do not initialize  { section .noinit };
 initialize by copy { readwrite };
 if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
@@ -80,15 +76,16 @@ if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
 
 place at address mem:__ROM0_BASE { readonly section .intvec };
 
-if (!isempty(ROM_region))
+if (!isempty(ROM1_region))
 {
-  place in ROM_region  { readonly };
+  place in ROM1_region { readonly };
 }
 
-if (!isempty(RAM_region))
+if (!isempty(RAM0_region))
 {
   define block CSTACK     with alignment = 8, size = __STACK_SIZE     { };
   define block PROC_STACK with alignment = 8, size = 0 { };
   define block HEAP       with alignment = 8, size = __HEAP_SIZE       { };
-  place in RAM_region  { readwrite, block CSTACK, block PROC_STACK, block HEAP };
+  place in RAM0_region { readwrite, block PROC_STACK, block HEAP };
+  place at end of RAM0_region { block CSTACK };
 }
diff --git a/example/FVP_Audio/board/Corstone-300/sse300_memmap_ns.h b/example/FVP_Audio/board/Corstone-300/sse300_memmap_ns.h
index d15a465..811a1c6 100644
--- a/example/FVP_Audio/board/Corstone-300/sse300_memmap_ns.h
+++ b/example/FVP_Audio/board/Corstone-300/sse300_memmap_ns.h
@@ -57,10 +57,10 @@
 #define SRAM_VM1_NS_LIMIT               (SRAM_VM1_NS_BASE + SRAM_VM1_NS_SIZE - 1)
 
 /*---------------------------------------------------------------------------*/
-/*                         Secure QSPI Flash Regions                         */
+/*                         Non-Secure QSPI Flash Regions                     */
 /*---------------------------------------------------------------------------*/
 
-/* QSPI Flash - Secure */
+/* QSPI Flash - Non-Secure */
 #define QSPI_FLASH_NS_BASE              0x28000000
 #define QSPI_FLASH_NS_SIZE              0x00800000    /* 8MB */
 #define QSPI_FLASH_NS_LIMIT             (QSPI_FLASH_NS_BASE + QSPI_FLASH_NS_SIZE - 1)
diff --git a/example/FVP_Audio/board/Corstone-310/sse310_memmap_ns.h b/example/FVP_Audio/board/Corstone-310/sse310_memmap_ns.h
index af37d33..ac33d65 100644
--- a/example/FVP_Audio/board/Corstone-310/sse310_memmap_ns.h
+++ b/example/FVP_Audio/board/Corstone-310/sse310_memmap_ns.h
@@ -57,10 +57,10 @@
 #define SRAM_VM1_NS_LIMIT               (SRAM_VM1_NS_BASE + SRAM_VM1_NS_SIZE - 1)
 
 /*---------------------------------------------------------------------------*/
-/*                         Secure QSPI Flash Regions                         */
+/*                         Non-Secure QSPI Flash Regions                     */
 /*---------------------------------------------------------------------------*/
 
-/* QSPI Flash - Secure */
+/* QSPI Flash - Non-Secure */
 #define QSPI_FLASH_NS_BASE              0x28000000
 #define QSPI_FLASH_NS_SIZE              0x00800000    /* 8MB */
 #define QSPI_FLASH_NS_LIMIT             (QSPI_FLASH_NS_BASE + QSPI_FLASH_NS_SIZE - 1)
diff --git a/example/FVP_Audio/board/Corstone-315/sse315_memmap_ns.h b/example/FVP_Audio/board/Corstone-315/sse315_memmap_ns.h
index 354f78b..0bfb56b 100644
--- a/example/FVP_Audio/board/Corstone-315/sse315_memmap_ns.h
+++ b/example/FVP_Audio/board/Corstone-315/sse315_memmap_ns.h
@@ -16,8 +16,8 @@
  * limitations under the License.
  *---------------------------------------------------------------------------*/
 
-#ifndef SSE320_MEMMAP_NS_H
-#define SSE320_MEMMAP_NS_H
+#ifndef SSE315_MEMMAP_NS_H
+#define SSE315_MEMMAP_NS_H
 
 /*============================================================================*/
 /*                           NON-SECURE MEMORY REGIONS                        */
@@ -99,4 +99,4 @@
 #define DDR4_6_NS_SIZE                  0x10000000    /* 256MB */
 #define DDR4_6_NS_LIMIT                 (DDR4_6_NS_BASE + DDR4_6_NS_SIZE - 1)
 
-#endif /* SSE320_MEMMAP_NS_H */
+#endif /* SSE315_MEMMAP_NS_H */
diff --git a/example/FVP_Audio/board/Corstone-315/sse315_memmap_s.h b/example/FVP_Audio/board/Corstone-315/sse315_memmap_s.h
index 42d7691..2d43b97 100644
--- a/example/FVP_Audio/board/Corstone-315/sse315_memmap_s.h
+++ b/example/FVP_Audio/board/Corstone-315/sse315_memmap_s.h
@@ -16,8 +16,8 @@
  * limitations under the License.
  *---------------------------------------------------------------------------*/
 
-#ifndef SSE320_MEMMAP_S_H
-#define SSE320_MEMMAP_S_H
+#ifndef SSE315_MEMMAP_S_H
+#define SSE315_MEMMAP_S_H
 
 /*============================================================================*/
 /*                             SECURE MEMORY REGIONS                          */
@@ -104,4 +104,4 @@
 #define DDR4_7_S_SIZE                   0x10000000    /* 256MB */
 #define DDR4_7_S_LIMIT                  (DDR4_7_S_BASE + DDR4_7_S_SIZE - 1)
 
-#endif /* SSE320_MEMMAP_S_H */
+#endif /* SSE315_MEMMAP_S_H */
diff --git a/example/FVP_Hello/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/example/FVP_Hello/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
index 4db620c..233a6de 100644
--- a/example/FVP_Hello/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
+++ b/example/FVP_Hello/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
@@ -48,9 +48,6 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
   ER_ROM1 __ROM1_BASE __ROM1_SIZE {
     *(+RO +XO)
   }
-}
-
-LR_RAM0 __RAM0_BASE NOCOMPRESS {
 
   RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
     *.o(.bss.noinit)
diff --git a/example/FVP_Hello/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src b/example/FVP_Hello/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src
index ea02d53..1a3548b 100644
--- a/example/FVP_Hello/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src
+++ b/example/FVP_Hello/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src
@@ -42,8 +42,6 @@ define memory mem with size = 4G;
   define region ROM3_region = [];
 #endif
 
-define region ROM_region = ROM0_region |  ROM1_region | ROM2_region | ROM3_region;
-
 #if __RAM0_SIZE > 0
   define region RAM0_region = mem:[from __RAM0_BASE to (__RAM0_BASE+__RAM0_SIZE-1)];
 #else
@@ -68,8 +66,6 @@ define region ROM_region = ROM0_region |  ROM1_region | ROM2_region | ROM3_regio
   define region RAM3_region = [];
 #endif
 
-define region RAM_region = RAM0_region | RAM1_region | RAM2_region | RAM3_region;
-
 do not initialize  { section .noinit };
 initialize by copy { readwrite };
 if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
@@ -80,15 +76,16 @@ if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
 
 place at address mem:__ROM0_BASE { readonly section .intvec };
 
-if (!isempty(ROM_region))
+if (!isempty(ROM1_region))
 {
-  place in ROM_region  { readonly };
+  place in ROM1_region { readonly };
 }
 
-if (!isempty(RAM_region))
+if (!isempty(RAM0_region))
 {
   define block CSTACK     with alignment = 8, size = __STACK_SIZE     { };
   define block PROC_STACK with alignment = 8, size = 0 { };
   define block HEAP       with alignment = 8, size = __HEAP_SIZE       { };
-  place in RAM_region  { readwrite, block CSTACK, block PROC_STACK, block HEAP };
+  place in RAM0_region { readwrite, block PROC_STACK, block HEAP };
+  place at end of RAM0_region { block CSTACK };
 }
diff --git a/example/FVP_Hello/board/Corstone-300/sse300_memmap_ns.h b/example/FVP_Hello/board/Corstone-300/sse300_memmap_ns.h
index d15a465..811a1c6 100644
--- a/example/FVP_Hello/board/Corstone-300/sse300_memmap_ns.h
+++ b/example/FVP_Hello/board/Corstone-300/sse300_memmap_ns.h
@@ -57,10 +57,10 @@
 #define SRAM_VM1_NS_LIMIT               (SRAM_VM1_NS_BASE + SRAM_VM1_NS_SIZE - 1)
 
 /*---------------------------------------------------------------------------*/
-/*                         Secure QSPI Flash Regions                         */
+/*                         Non-Secure QSPI Flash Regions                     */
 /*---------------------------------------------------------------------------*/
 
-/* QSPI Flash - Secure */
+/* QSPI Flash - Non-Secure */
 #define QSPI_FLASH_NS_BASE              0x28000000
 #define QSPI_FLASH_NS_SIZE              0x00800000    /* 8MB */
 #define QSPI_FLASH_NS_LIMIT             (QSPI_FLASH_NS_BASE + QSPI_FLASH_NS_SIZE - 1)
diff --git a/example/FVP_Hello/board/Corstone-310/sse310_memmap_ns.h b/example/FVP_Hello/board/Corstone-310/sse310_memmap_ns.h
index af37d33..ac33d65 100644
--- a/example/FVP_Hello/board/Corstone-310/sse310_memmap_ns.h
+++ b/example/FVP_Hello/board/Corstone-310/sse310_memmap_ns.h
@@ -57,10 +57,10 @@
 #define SRAM_VM1_NS_LIMIT               (SRAM_VM1_NS_BASE + SRAM_VM1_NS_SIZE - 1)
 
 /*---------------------------------------------------------------------------*/
-/*                         Secure QSPI Flash Regions                         */
+/*                         Non-Secure QSPI Flash Regions                     */
 /*---------------------------------------------------------------------------*/
 
-/* QSPI Flash - Secure */
+/* QSPI Flash - Non-Secure */
 #define QSPI_FLASH_NS_BASE              0x28000000
 #define QSPI_FLASH_NS_SIZE              0x00800000    /* 8MB */
 #define QSPI_FLASH_NS_LIMIT             (QSPI_FLASH_NS_BASE + QSPI_FLASH_NS_SIZE - 1)
diff --git a/example/FVP_Hello/board/Corstone-315/sse315_memmap_ns.h b/example/FVP_Hello/board/Corstone-315/sse315_memmap_ns.h
index 354f78b..0bfb56b 100644
--- a/example/FVP_Hello/board/Corstone-315/sse315_memmap_ns.h
+++ b/example/FVP_Hello/board/Corstone-315/sse315_memmap_ns.h
@@ -16,8 +16,8 @@
  * limitations under the License.
  *---------------------------------------------------------------------------*/
 
-#ifndef SSE320_MEMMAP_NS_H
-#define SSE320_MEMMAP_NS_H
+#ifndef SSE315_MEMMAP_NS_H
+#define SSE315_MEMMAP_NS_H
 
 /*============================================================================*/
 /*                           NON-SECURE MEMORY REGIONS                        */
@@ -99,4 +99,4 @@
 #define DDR4_6_NS_SIZE                  0x10000000    /* 256MB */
 #define DDR4_6_NS_LIMIT                 (DDR4_6_NS_BASE + DDR4_6_NS_SIZE - 1)
 
-#endif /* SSE320_MEMMAP_NS_H */
+#endif /* SSE315_MEMMAP_NS_H */
diff --git a/example/FVP_Hello/board/Corstone-315/sse315_memmap_s.h b/example/FVP_Hello/board/Corstone-315/sse315_memmap_s.h
index 42d7691..2d43b97 100644
--- a/example/FVP_Hello/board/Corstone-315/sse315_memmap_s.h
+++ b/example/FVP_Hello/board/Corstone-315/sse315_memmap_s.h
@@ -16,8 +16,8 @@
  * limitations under the License.
  *---------------------------------------------------------------------------*/
 
-#ifndef SSE320_MEMMAP_S_H
-#define SSE320_MEMMAP_S_H
+#ifndef SSE315_MEMMAP_S_H
+#define SSE315_MEMMAP_S_H
 
 /*============================================================================*/
 /*                             SECURE MEMORY REGIONS                          */
@@ -104,4 +104,4 @@
 #define DDR4_7_S_SIZE                   0x10000000    /* 256MB */
 #define DDR4_7_S_LIMIT                  (DDR4_7_S_BASE + DDR4_7_S_SIZE - 1)
 
-#endif /* SSE320_MEMMAP_S_H */
+#endif /* SSE315_MEMMAP_S_H */
diff --git a/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
index 4db620c..233a6de 100644
--- a/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
+++ b/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src
@@ -48,9 +48,6 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
   ER_ROM1 __ROM1_BASE __ROM1_SIZE {
     *(+RO +XO)
   }
-}
-
-LR_RAM0 __RAM0_BASE NOCOMPRESS {
 
   RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
     *.o(.bss.noinit)
diff --git a/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src b/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src
new file mode 100644
index 0000000..545300e
--- /dev/null
+++ b/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src
@@ -0,0 +1,386 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright © 2019 Keith Packard
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE   ( 8 )
+#else
+#define __STACKSEAL_SIZE   ( 0 )
+#endif
+
+/* ----------------------------------------------------------------------------
+  Memory definition
+ *----------------------------------------------------------------------------*/
+MEMORY
+{
+  ROM0  (rx!w)  : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE
+#if __ROM1_SIZE > 0
+  ROM1  (rx!w)  : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE
+#endif
+#if __ROM2_SIZE > 0
+  ROM2  (rx!w)  : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE
+#endif
+#if __ROM3_SIZE > 0
+  ROM3  (rx!w)  : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE
+#endif
+
+  RAM0  (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE
+#if __RAM1_SIZE > 0
+  RAM1  (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE
+#endif
+#if __RAM2_SIZE > 0
+  RAM2  (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE
+#endif
+#if __RAM3_SIZE > 0
+  RAM3  (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE
+#endif
+}
+
+ENTRY(Reset_Handler)
+
+PHDRS
+{
+    boot PT_LOAD;
+    text PT_LOAD;
+    ram PT_LOAD;
+    ram_init PT_LOAD;
+    tls PT_TLS;
+}
+
+SECTIONS
+{
+    .init : {
+        KEEP (*(.vectors))
+
+        /* Disable by default
+         *
+         * *.init.enter contains a vector table provided by picolibc,
+         * whereas CMSIS already provides a vector table via .vectors
+         */
+        /*
+        KEEP (*(.text.init.enter))
+        KEEP (*(.data.init.enter))
+        */
+
+        KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*)))
+    } >ROM0 AT>ROM0 :boot
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    .veneers :
+    {
+        . = ALIGN(32);
+        KEEP(*(.gnu.sgstubs))
+    } > ROM0 AT>ROM0 :boot
+#endif
+
+    .text : {
+
+        /* code */
+        *(.text.unlikely .text.unlikely.*)
+        *(.text.startup .text.startup.*)
+        *(.text .text.* .opd .opd.*)
+        *(.gnu.linkonce.t.*)
+        KEEP (*(.fini .fini.*))
+        __text_end = .;
+
+        PROVIDE (__etext = __text_end);
+        PROVIDE (_etext = __text_end);
+        PROVIDE (etext = __text_end);
+
+        /* read-only data */
+        *(.rdata)
+        *(.rodata .rodata.*)
+        *(.gnu.linkonce.r.*)
+
+        *(.srodata.cst16)
+        *(.srodata.cst8)
+        *(.srodata.cst4)
+        *(.srodata.cst2)
+        *(.srodata .srodata.*)
+        *(.data.rel.ro .data.rel.ro.*)
+        *(.got .got.*)
+
+        /* Need to pre-align so that the symbols come after padding */
+        . = ALIGN(8);
+
+        /* lists of constructors and destructors */
+        PROVIDE_HIDDEN ( __bothinit_array_start = . );
+        PROVIDE_HIDDEN ( __preinit_array_start = . );
+        KEEP (*(.preinit_array))
+        PROVIDE_HIDDEN ( __preinit_array_end = . );
+
+        PROVIDE_HIDDEN ( __init_array_start = . );
+        KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+        KEEP (*(.init_array .ctors))
+        PROVIDE_HIDDEN ( __init_array_end = . );
+        PROVIDE_HIDDEN ( __bothinit_array_end = . );
+
+        PROVIDE_HIDDEN ( __fini_array_start = . );
+        KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+        KEEP (*(.fini_array .dtors))
+        PROVIDE_HIDDEN ( __fini_array_end = . );
+
+    } >ROM1 AT>ROM1 :text
+
+    .toc : {
+        *(.toc .toc.*)
+    } >ROM1 AT>ROM1 :text
+
+    /* additional sections when compiling with C++ exception support */
+
+    .except_ordered : {
+        *(.gcc_except_table *.gcc_except_table.*)
+        KEEP (*(.eh_frame .eh_frame.*))
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } >ROM1 AT>ROM1 :text
+
+    .except_unordered : {
+        . = ALIGN(8);
+
+        PROVIDE(__exidx_start = .);
+        *(.ARM.exidx*)
+        PROVIDE(__exidx_end = .);
+    } >ROM1 AT>ROM1 :text
+
+
+    /*
+     * Data values which are preserved across reset
+     */
+    .preserve (NOLOAD) : {
+        PROVIDE(__preserve_start__ = .);
+        KEEP(*(SORT_BY_NAME(.preserve.*)))
+        KEEP(*(.preserve))
+        PROVIDE(__preserve_end__ = .);
+    } >RAM0 AT>RAM0 :ram
+
+    .data :  {
+        *(.data .data.*)
+        *(.gnu.linkonce.d.*)
+
+        /* Need to pre-align so that the symbols come after padding */
+        . = ALIGN(8);
+
+        PROVIDE( __global_pointer$ = . + 0x800 );
+        *(.sdata .sdata.* .sdata2.*)
+        *(.gnu.linkonce.s.*)
+    } >RAM0 AT>ROM1 :ram_init
+    PROVIDE(__data_start = ADDR(.data));
+    PROVIDE(__data_source = LOADADDR(.data));
+
+    /* Thread local initialized data. This gets
+     * space allocated as it is expected to be placed
+     * in ram to be used as a template for TLS data blocks
+     * allocated at runtime. We're slightly abusing that
+     * by placing the data in flash where it will be copied
+     * into the allocate ram addresses by the existing
+     * data initialization code in crt0
+     */
+    .tdata :  {
+        *(.tdata .tdata.* .gnu.linkonce.td.*)
+        PROVIDE(__data_end = .);
+        PROVIDE(__tdata_end = .);
+    } >RAM0 AT>ROM1 :tls :ram_init
+    PROVIDE( __tls_base = ADDR(.tdata));
+    PROVIDE( __tdata_start = ADDR(.tdata));
+    PROVIDE( __tdata_source = LOADADDR(.tdata) );
+    PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) );
+    PROVIDE( __data_source_end = __tdata_source_end );
+    PROVIDE( __tdata_size = SIZEOF(.tdata) );
+    PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) );
+
+    PROVIDE( __edata = __data_end );
+    PROVIDE( _edata = __data_end );
+    PROVIDE( edata = __data_end );
+    PROVIDE( __data_size = __data_end - __data_start );
+    PROVIDE( __data_source_size = __data_source_end - __data_source );
+
+    .tbss (NOLOAD) : {
+        *(.tbss .tbss.* .gnu.linkonce.tb.*)
+        *(.tcommon)
+        PROVIDE( __tls_end = . );
+        PROVIDE( __tbss_end = . );
+    } >RAM0 AT>RAM0 :tls :ram
+    PROVIDE( __bss_start = ADDR(.tbss));
+    PROVIDE( __tbss_start = ADDR(.tbss));
+    PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) );
+    PROVIDE( __tbss_size = SIZEOF(.tbss) );
+    PROVIDE( __tls_size = __tls_end - __tls_base );
+    PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) );
+    PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) );
+    PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) );
+
+    /*
+     * The linker special cases .tbss segments which are
+     * identified as segments which are not loaded and are
+     * thread_local.
+     *
+     * For these segments, the linker does not advance 'dot'
+     * across them.  We actually need memory allocated for tbss,
+     * so we create a special segment here just to make room
+     */
+    /*
+    .tbss_space (NOLOAD) : {
+        . = ADDR(.tbss);
+        . = . + SIZEOF(.tbss);
+    } >RAM0 AT>RAM0 :ram
+    */
+
+    .bss (NOLOAD) : {
+        *(.sbss*)
+        *(.gnu.linkonce.sb.*)
+        *(.bss .bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+
+        /* Align the end of this section, so next can start on aligned address */
+        . = ALIGN(8);
+        __bss_end = .;
+    } >RAM0 AT>RAM0 :ram
+    PROVIDE( __non_tls_bss_start = ADDR(.bss) );
+    PROVIDE( __bss_size = __bss_end - __bss_start );
+
+    /* This section contains data that is not initialized during load,
+       or during the application's initialization sequence. */
+    .noinit (NOLOAD) : {
+        __noinit_start__ = .;
+        *(.noinit)
+        *(.noinit.*)
+
+        /* Align the end of this section, so next (heap) can start on aligned address */
+        . = ALIGN(8);
+        __noinit_end__ = .;
+    } >RAM0 AT>RAM0 :ram
+
+    PROVIDE( __end = . );
+    PROVIDE( _end = . );
+    PROVIDE( end = . );
+
+    /* Make the rest of memory available for heap storage */
+    PROVIDE (__heap_start = __end);
+#ifdef __HEAP_SIZE
+    PROVIDE (__heap_end = __heap_start + __HEAP_SIZE);
+    PROVIDE (__heap_size = __HEAP_SIZE);
+#else
+    PROVIDE (__heap_end = __stack - __STACK_SIZE);
+    PROVIDE (__heap_size = __heap_end - __heap_start);
+#endif
+    .heap (NOLOAD) : {
+        . += __heap_size;
+    } >RAM0 :ram
+
+    /* Define a stack region to make sure it fits in memory */
+    PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE);
+    PROVIDE(__stack_limit = __stack - __STACK_SIZE);
+    .stack (__stack_limit) (NOLOAD) : {
+        . += __STACK_SIZE;
+    } >RAM0 :ram
+
+#if __STACKSEAL_SIZE > 0
+    PROVIDE(__stack_seal = __stack);
+    .stackseal (__stack) (NOLOAD) :
+    {
+        . += __STACKSEAL_SIZE;
+    } >RAM0 :ram
+#endif
+
+    /* Throw away C++ exception handling information */
+
+    /*
+
+    /DISCARD/ : {
+        *(.note .note.*)
+        *(.eh_frame .eh_frame.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.ARM.exidx*)
+    }
+
+    */
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
+    /* DWARF debug sections.
+       Symbols in the DWARF debugging sections are relative to the beginning
+       of the section so we begin them at 0.  */
+    /* DWARF 1.  */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions.  */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2.  */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2.  */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions.  */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+    /* DWARF 3.  */
+    .debug_pubtypes 0 : { *(.debug_pubtypes) }
+    .debug_ranges   0 : { *(.debug_ranges) }
+    /* DWARF 5.  */
+    .debug_addr     0 : { *(.debug_addr) }
+    .debug_line_str 0 : { *(.debug_line_str) }
+    .debug_loclists 0 : { *(.debug_loclists) }
+    .debug_macro    0 : { *(.debug_macro) }
+    .debug_names    0 : { *(.debug_names) }
+    .debug_rnglists 0 : { *(.debug_rnglists) }
+    .debug_str_offsets 0 : { *(.debug_str_offsets) }
+    .debug_sup      0 : { *(.debug_sup) }
+    .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+}
+/*
+ * Check that sections that are copied from flash to RAM have matching
+ * padding, so that a single memcpy() of __data_size copies the correct bytes.
+ */
+ASSERT( __data_size == __data_source_size,
+    "ERROR: .data/.tdata flash size does not match RAM size");
diff --git a/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src b/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src
index ea02d53..1a3548b 100644
--- a/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src
+++ b/example/FVP_Video/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src
@@ -42,8 +42,6 @@ define memory mem with size = 4G;
   define region ROM3_region = [];
 #endif
 
-define region ROM_region = ROM0_region |  ROM1_region | ROM2_region | ROM3_region;
-
 #if __RAM0_SIZE > 0
   define region RAM0_region = mem:[from __RAM0_BASE to (__RAM0_BASE+__RAM0_SIZE-1)];
 #else
@@ -68,8 +66,6 @@ define region ROM_region = ROM0_region |  ROM1_region | ROM2_region | ROM3_regio
   define region RAM3_region = [];
 #endif
 
-define region RAM_region = RAM0_region | RAM1_region | RAM2_region | RAM3_region;
-
 do not initialize  { section .noinit };
 initialize by copy { readwrite };
 if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
@@ -80,15 +76,16 @@ if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
 
 place at address mem:__ROM0_BASE { readonly section .intvec };
 
-if (!isempty(ROM_region))
+if (!isempty(ROM1_region))
 {
-  place in ROM_region  { readonly };
+  place in ROM1_region { readonly };
 }
 
-if (!isempty(RAM_region))
+if (!isempty(RAM0_region))
 {
   define block CSTACK     with alignment = 8, size = __STACK_SIZE     { };
   define block PROC_STACK with alignment = 8, size = 0 { };
   define block HEAP       with alignment = 8, size = __HEAP_SIZE       { };
-  place in RAM_region  { readwrite, block CSTACK, block PROC_STACK, block HEAP };
+  place in RAM0_region { readwrite, block PROC_STACK, block HEAP };
+  place at end of RAM0_region { block CSTACK };
 }
diff --git a/example/FVP_Video/board/Corstone-300/sse300_memmap_ns.h b/example/FVP_Video/board/Corstone-300/sse300_memmap_ns.h
index d15a465..811a1c6 100644
--- a/example/FVP_Video/board/Corstone-300/sse300_memmap_ns.h
+++ b/example/FVP_Video/board/Corstone-300/sse300_memmap_ns.h
@@ -57,10 +57,10 @@
 #define SRAM_VM1_NS_LIMIT               (SRAM_VM1_NS_BASE + SRAM_VM1_NS_SIZE - 1)
 
 /*---------------------------------------------------------------------------*/
-/*                         Secure QSPI Flash Regions                         */
+/*                         Non-Secure QSPI Flash Regions                     */
 /*---------------------------------------------------------------------------*/
 
-/* QSPI Flash - Secure */
+/* QSPI Flash - Non-Secure */
 #define QSPI_FLASH_NS_BASE              0x28000000
 #define QSPI_FLASH_NS_SIZE              0x00800000    /* 8MB */
 #define QSPI_FLASH_NS_LIMIT             (QSPI_FLASH_NS_BASE + QSPI_FLASH_NS_SIZE - 1)
diff --git a/example/FVP_Video/board/Corstone-310/sse310_memmap_ns.h b/example/FVP_Video/board/Corstone-310/sse310_memmap_ns.h
index af37d33..ac33d65 100644
--- a/example/FVP_Video/board/Corstone-310/sse310_memmap_ns.h
+++ b/example/FVP_Video/board/Corstone-310/sse310_memmap_ns.h
@@ -57,10 +57,10 @@
 #define SRAM_VM1_NS_LIMIT               (SRAM_VM1_NS_BASE + SRAM_VM1_NS_SIZE - 1)
 
 /*---------------------------------------------------------------------------*/
-/*                         Secure QSPI Flash Regions                         */
+/*                         Non-Secure QSPI Flash Regions                     */
 /*---------------------------------------------------------------------------*/
 
-/* QSPI Flash - Secure */
+/* QSPI Flash - Non-Secure */
 #define QSPI_FLASH_NS_BASE              0x28000000
 #define QSPI_FLASH_NS_SIZE              0x00800000    /* 8MB */
 #define QSPI_FLASH_NS_LIMIT             (QSPI_FLASH_NS_BASE + QSPI_FLASH_NS_SIZE - 1)
diff --git a/example/FVP_Video/board/Corstone-315/sse315_memmap_ns.h b/example/FVP_Video/board/Corstone-315/sse315_memmap_ns.h
index 354f78b..0bfb56b 100644
--- a/example/FVP_Video/board/Corstone-315/sse315_memmap_ns.h
+++ b/example/FVP_Video/board/Corstone-315/sse315_memmap_ns.h
@@ -16,8 +16,8 @@
  * limitations under the License.
  *---------------------------------------------------------------------------*/
 
-#ifndef SSE320_MEMMAP_NS_H
-#define SSE320_MEMMAP_NS_H
+#ifndef SSE315_MEMMAP_NS_H
+#define SSE315_MEMMAP_NS_H
 
 /*============================================================================*/
 /*                           NON-SECURE MEMORY REGIONS                        */
@@ -99,4 +99,4 @@
 #define DDR4_6_NS_SIZE                  0x10000000    /* 256MB */
 #define DDR4_6_NS_LIMIT                 (DDR4_6_NS_BASE + DDR4_6_NS_SIZE - 1)
 
-#endif /* SSE320_MEMMAP_NS_H */
+#endif /* SSE315_MEMMAP_NS_H */
diff --git a/example/FVP_Video/board/Corstone-315/sse315_memmap_s.h b/example/FVP_Video/board/Corstone-315/sse315_memmap_s.h
index 42d7691..2d43b97 100644
--- a/example/FVP_Video/board/Corstone-315/sse315_memmap_s.h
+++ b/example/FVP_Video/board/Corstone-315/sse315_memmap_s.h
@@ -16,8 +16,8 @@
  * limitations under the License.
  *---------------------------------------------------------------------------*/
 
-#ifndef SSE320_MEMMAP_S_H
-#define SSE320_MEMMAP_S_H
+#ifndef SSE315_MEMMAP_S_H
+#define SSE315_MEMMAP_S_H
 
 /*============================================================================*/
 /*                             SECURE MEMORY REGIONS                          */
@@ -104,4 +104,4 @@
 #define DDR4_7_S_SIZE                   0x10000000    /* 256MB */
 #define DDR4_7_S_LIMIT                  (DDR4_7_S_BASE + DDR4_7_S_SIZE - 1)
 
-#endif /* SSE320_MEMMAP_S_H */
+#endif /* SSE315_MEMMAP_S_H */