diff --git a/config.local/arm64/config.sonic-aspeed b/config.local/arm64/config.sonic-aspeed index 4fd978a..18bc857 100644 --- a/config.local/arm64/config.sonic-aspeed +++ b/config.local/arm64/config.sonic-aspeed @@ -105,10 +105,10 @@ CONFIG_CRYPTO_DEV_ASPEED=y # CONFIG_CRYPTO_DEV_ASPEED_HACE is not set # CONFIG_CRYPTO_DEV_ASPEED_RSSS is not set # CONFIG_CRYPTO_DEV_ASPEED_ECDSA is not set +CONFIG_MODVERSIONS=y ###-> nvidia_aspeed_bmc-start -CONFIG_MODVERSIONS=y -CONFIG_MCTP=y +CONFIG_MTD_PHRAM=y CONFIG_CHR_DEV_SG=y CONFIG_REALTEK_PHY=m CONFIG_USB_USBNET=y @@ -145,7 +145,6 @@ CONFIG_PSTORE_RAM=y CONFIG_LSUSB=y CONFIG_USB_ETH_RNDIS=y CONFIG_USB_ASPEED=y -CONFIG_SPI_ASPEED_TXRX=y CONFIG_SPI_ASPEED_SMC=y CONFIG_SPI_FMC=m CONFIG_FIXED_PHY_APPLY=y @@ -153,20 +152,13 @@ CONFIG_FIXED_PHY_SPEED=100 CONFIG_FIXED_PHY_FULL_DUPLEX=y CONFIG_FTGMAC100_FIXED_PHY_SPEED=100 CONFIG_FTGMAC100_FIXED_PHY_FULL_DUPLEX=1 -CONFIG_ASPEED_MCTP=y CONFIG_JTAG=y CONFIG_JTAG_ASPEED=y -CONFIG_COMMON_CLK_AST2700=y -CONFIG_AST2700_RTC_OVER_ESPI=y CONFIG_AST2700_MBOX=y CONFIG_RTL_RGMII_SGMII_3809=y CONFIG_HID_CP2112=m CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_ASPEED_SGPIO=y -CONFIG_ASPEED_LPC_SNOOP=y -CONFIG_AST2700_ESPI=y CONFIG_MISC_DEVICES=y -CONFIG_ASPEED_UART_ROUTING=y CONFIG_FTGMAC100=m CONFIG_SENSORS_LM25066=m CONFIG_SENSORS_MP2855=m @@ -194,4 +186,3 @@ CONFIG_NVSW_BMC_HID162=m CONFIG_I2C_MUX_REGMAP=y CONFIG_PCIE_PME=n ###-> nvidia_aspeed_bmc-end - diff --git a/patches-sonic/0001-mlxbf-bootctl-Constify-struct-bin_attribute.patch b/patches-sonic/0001-mlxbf-bootctl-Constify-struct-bin_attribute.patch deleted file mode 100644 index 130f8a4..0000000 --- a/patches-sonic/0001-mlxbf-bootctl-Constify-struct-bin_attribute.patch +++ /dev/null @@ -1,36 +0,0 @@ -From cad481488093e440217f6a93e45fe4fa03a77000 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= -Date: Sun, 15 Dec 2024 14:25:40 +0100 -Subject: [PATCH 01/78] mlxbf-bootctl: Constify 'struct bin_attribute' -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The sysfs core now allows instances of 'struct bin_attribute' to be -moved into read-only memory. Make use of that to protect them against -accidental or malicious modifications. - -Signed-off-by: Thomas Weißschuh -Link: https://lore.kernel.org/r/20241215-sysfs-const-bin_attr-mellanox-v1-1-b6fe4f68e2ca@weissschuh.net -Reviewed-by: Ilpo Järvinen -Signed-off-by: Ilpo Järvinen ---- - drivers/platform/mellanox/mlxbf-bootctl.c | 2 +- - 1 file changed, 1 insertions(+), 1 deletions(-) - -diff --git a/drivers/platform/mellanox/mlxbf-bootctl.c b/drivers/platform/mellanox/mlxbf-bootctl.c -index dd5f370..7e246dd 100644 ---- a/drivers/platform/mellanox/mlxbf-bootctl.c -+++ b/drivers/platform/mellanox/mlxbf-bootctl.c -@@ -939,7 +939,7 @@ MODULE_DEVICE_TABLE(acpi, mlxbf_bootctl_acpi_ids); - - static ssize_t mlxbf_bootctl_bootfifo_read(struct file *filp, - struct kobject *kobj, -- struct bin_attribute *bin_attr, -+ const struct bin_attribute *bin_attr, - char *buf, loff_t pos, - size_t count) - { --- -2.8.4 - diff --git a/patches-sonic/0008-arm64-dts-aspeed-spc6-bmc-ext-phram-env-tpm-i3c-pull.patch b/patches-sonic/0008-arm64-dts-aspeed-spc6-bmc-ext-phram-env-tpm-i3c-pull.patch new file mode 100644 index 0000000..fdcdd35 --- /dev/null +++ b/patches-sonic/0008-arm64-dts-aspeed-spc6-bmc-ext-phram-env-tpm-i3c-pull.patch @@ -0,0 +1,160 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Dvir Zaguri +Date: Sun, 31 May 2026 10:15:00 +0300 +Subject: [PATCH 6.12 1/1] arm64: dts: aspeed: spc6-bmc: phram-env, TPM init, + GPIO expander reset, I3C pull-ups + +Extend arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc.dts +(AST2700-A2 SPC6 CPU BMC) with four downstream fixes taken from +the OpenBMC Switch-26.05-1_br branch. Only the kernel DTS hunks +from each commit are taken; the matching userspace / U-Boot / +kconfig changes live in their own layers and are out of scope. + + 51f092d656fbe81d704036246fad43a186d008fb + "L1 Switch: SPC6 AST2700 BMC: move recovery counter to phram-env" + Dmitrijs Novikovs , May 12 2026 + + * Reserve a 4 KiB phram region (phram_env @ 0x4_237ff000), one + page below bmc-dev0, inside reserved-memory. fw_env now points + at /dev/mtd/by-name/phram-env so the recovery counter and the + rest of the U-Boot env survive warm boots. + + 2c97dad11108b1ceaedadd0762f3ef342b06abe9 + "L1 Switch: SPC6 AST2700 BMC: fix TPM GPIO init" + Sergejs Hatinecs , May 28 2026 + + * Add two gpio-hogs (spi-buf-oe, spi-tpm-buf-oe) on the i2c5 + pcal6524 (exp0) to drive GP_BMC_SPI_BUF_OE_L (pin 4) and + GP_BMC_SPI_TPM_BUF_OE_L (pin 5) low at gpiochip registration, + enabling the SPI and SPI/TPM level shifters before any SPI + probe touches the bus. + * Add a private buf-en-link-gpios property on tpm@1 pointing at + the same two exp0 pins. The property is intentionally NOT + consumed by any driver -- it exists solely as an fw_devlink + ordering hint so tpm@1 cannot probe until exp0 has probed and + its hogs have run. This kills the "no TPM found" race between + the i2c5 and spi0 buses. + + d406755fdf8bd1421095b6470bc1ca47e35697b6 + "L1 Switch: SPC6 AST2700 BMC: fix GPIO expander" + Sergejs Hatinecs , May 29 2026 + + * Add reset-gpios to the i2c5 pcal6524 (exp0) pointing at + GP_BMC_GPIO_EXP_RESET_L (gpio1 bank S, line 0, active-low), + so the pcal6524 driver pulse-resets the expander at probe and + starts it in a known state. Without this the expander could + stay wedged from a previous boot, breaking the SPI/TPM buffer + hogs, the mdio2 PHY reset (driven through &exp0 10) and the + WP / MUX-select lines that ride on the same expander. + + 2e6c7a8a27033a696505425384d8f5551aa86a36 + "L1 Switch: SPC6 AST2700: Enable I3C internal pull-ups via DT" + Dmitrijs Novikovs , May 15 2026 + + * Add internal-pullup = <1> to &i3c1 so the SoC drives the I3C + bus pull-ups and the controller comes up at boot without the + previous late user-space bind workaround. + +Signed-off-by: Dvir Zaguri +--- + .../boot/dts/aspeed/aspeed-nvidia-spc6-bmc.dts | 59 ++++++++++++++++++++++ + 1 file changed, 59 insertions(+) + +diff --git a/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc.dts b/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc.dts +--- a/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc.dts ++++ b/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc.dts +@@ -29,6 +29,15 @@ + ranges; + + #include "ast2700-reserved-mem.dtsi" ++ ++ // (before bmc-dev0 @0x423800000). ++ // Persistent phram region for fw_env variables across warm boots. ++ phram_env: phram-env@4237ff000 { ++ compatible = "phram"; ++ label = "phram-env"; ++ reg = <0x00000004 0x237ff000 0x0 0x00001000>; ++ no-map; ++ }; + }; + }; + +@@ -55,6 +64,30 @@ + compatible = "st,st33htpm-spi", "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <10000000>; ++ /* ++ * NOTE: this property is NOT consumed by any driver. Stock ++ * tpm_tis_spi (and all other drivers matching the compatibles ++ * above) does not call gpiod_get() for this name. That is ++ * intentional -- the SPI/TPM level shifters are enabled by the ++ * gpio-hogs on exp0 (see below), not by this device. ++ * ++ * It is kept purely as an fw_devlink ordering hint: any property ++ * whose name ends in "-gpios" is parsed by the DT core to build ++ * a supplier/consumer link. The phandle to exp0 therefore makes ++ * exp0 a supplier of tpm@1, so tpm@1 is not probed until the ++ * pcal6524 has probed and its hogs have run. Without this hint ++ * there is no ordering between the i2c5 and spi0 buses, and the ++ * TPM could be accessed before the buffers are enabled (races to ++ * "no TPM found"). Do not delete it. ++ * ++ * The property name is deliberately a private one ++ * ("buf-en-link-gpios") that no upstream driver consumes. If ++ * the property were called "enable-gpios" and a future kernel ++ * added gpiod_get(dev, "enable", ...) to tpm_tis_spi, it would ++ * collide with the hogs and fail -EBUSY. ++ */ ++ buf-en-link-gpios = <&exp0 4 GPIO_ACTIVE_LOW>, ++ <&exp0 5 GPIO_ACTIVE_LOW>; + }; + }; + +@@ -243,6 +276,7 @@ + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; ++ reset-gpios = <&gpio1 ASPEED_GPIO(S, 0) GPIO_ACTIVE_LOW>; /*GPIO_BMC_GPIO_EXP_RESET_L*/ + + gpio-line-names = + "RSRVD_0", "GP_EROT_RST_IN_L", +@@ -257,6 +291,30 @@ + "RSRVD_7", "GP_PROD_CS_FLASH0_EN", + "RSRVD_8", "GP_PROD_CS_FLASH1_EN", + "RSRVD_9", "RSRVD_10"; ++ /* ++ * Enable the SPI/TPM level shifters at gpiochip registration, ++ * i.e. during this node's probe -- before tpm@1 (ordered after ++ * us via the buf-en-link-gpios phandle above) touches ++ * the bus. ++ * ++ * POLARITY: these nets are active-low (..._OE_L), so physical low ++ * enables the buffer. In a gpio-hog, output-low/output-high are ++ * LOGICAL values and are inverted by GPIO_ACTIVE_LOW. Therefore ++ * "output-high" = logical 1 = physical low = buffer ENABLED. ++ * Using "output-low" here would drive the pin high and DISABLE ++ * the buffers -- the opposite of what we want. ++ */ ++ spi-buf-oe { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_LOW>; /* GP_BMC_SPI_BUF_OE_L */ ++ output-high; /* -> physical low -> enabled */ ++ }; ++ ++ spi-tpm-buf-oe { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_LOW>; /* GP_BMC_SPI_TPM_BUF_OE_L */ ++ output-high; /* -> physical low -> enabled */ ++ }; + }; + }; + +@@ -463,5 +521,6 @@ + status = "okay"; + pinctrl-names = "default"; + i3c-scl-hz = <12500000>; ++ internal-pullup = <1>; + mctp-controller; + }; +-- +2.34.1 diff --git a/patches-sonic/0009-arm64-dts-aspeed-split-SPC6-BMC-DTS-for-SONiC-and-Op.patch b/patches-sonic/0009-arm64-dts-aspeed-split-SPC6-BMC-DTS-for-SONiC-and-Op.patch new file mode 100644 index 0000000..6307692 --- /dev/null +++ b/patches-sonic/0009-arm64-dts-aspeed-split-SPC6-BMC-DTS-for-SONiC-and-Op.patch @@ -0,0 +1,620 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Thu, 4 Jun 2026 11:03:21 +0300 +Subject: [PATCH 6.12 1/1] arm64: dts: aspeed: split SPC6 BMC DTS for SONiC + and OpenBMC boot +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +SONiC and OpenBMC use different rootfs boot paths on the same board. + +OpenBMC loads rootfs from SPI via phram: +(phram.phram=ramrofs,0x403920000,… and root=/dev/ram). +The device tree therefore reserves ramrofs@403920000. + +SONiC boots from eMMC (root=UUID, squashfs loop) and does not use +phram. Keeping ramrofs in the SONiC DTB causes early boot failures +when the kernel cannot reserve that region (it overlaps the kernel +load window around 0x403000000). + +Add SONiC-specific irot/sunda fragments without the ramrofs +reservation and build aspeed-nvidia-spc6-bmc.dtb from them so +SONiC FIT configs stay unchanged. +Add aspeed-nvidia-spc6-bmc-openbmc.dts for OpenBMC (phram/SPI) +with the existing ramrofs node and irot.dtsi. + +Signed-off-by: Vadim Pasternak +--- + .../aspeed/aspeed-nvidia-spc6-bmc-openbmc.dts | 527 ++++++++++++++++++ + .../dts/aspeed/aspeed-nvidia-spc6-bmc.dts | 2 +- + .../dts/aspeed/nvidia-ast27xx-irot-sonic.dtsi | 14 + + .../aspeed/nvidia-ast27xx-sunda-sonic.dtsi | 8 + + 4 files changed, 549 insertions(+), 1 deletion(-) + create mode 100644 arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc-openbmc.dts + create mode 100644 arch/arm64/boot/dts/aspeed/nvidia-ast27xx-irot-sonic.dtsi + create mode 100644 arch/arm64/boot/dts/aspeed/nvidia-ast27xx-sunda-sonic.dtsi + +diff --git a/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc-openbmc.dts b/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc-openbmc.dts +new file mode 100644 +index 000000000..e825c106d +--- /dev/null ++++ b/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc-openbmc.dts +@@ -0,0 +1,527 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/dts-v1/; ++ ++#include "aspeed-nvidia-spc6-bmc-core.dtsi" ++#include ++#include ++#include ++#include "nvidia-ast27xx-sunda.dtsi" ++ ++#define PCIE0_EP 1 // 1: EP, 0: RC ++ ++/ { ++ model = "AST2700-A2 SPC6 CPU BMC"; ++ compatible = "aspeed,ast2700"; ++ ++ aliases { ++ rtc0 = &ext_rtc; /* Forces PCF85053A to be rtc0 */ ++ rtc1 = &rtc; /* Moves Aspeed Internal RTC to rtc1 */ ++ }; ++ ++ chosen { ++ stdout-path = &uart12; ++ bootargs = "console=ttyS12,115200 earlyprintk"; ++ }; ++ ++ memory@400000000 { ++ device_type = "memory"; ++ reg = <0x4 0x00000000 0x0 0x40000000>; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ #include "ast2700-reserved-mem.dtsi" ++ ++ // (before bmc-dev0 @0x423800000). ++ // Persistent phram region for fw_env variables across warm boots. ++ phram_env: phram-env@4237ff000 { ++ compatible = "phram"; ++ label = "phram-env"; ++ reg = <0x00000004 0x237ff000 0x0 0x00001000>; ++ no-map; ++ }; ++ }; ++}; ++ ++/* ++ * SPI0: BIOS recovery (CS0, CPLD selects which flash) and TPM (CS1, AST2700 only). ++ * AST2700 uses &spi0; AST2600 uses &spi1raw. ++ * Remove default flash@0/flash@1 from dtsi so spidev and tpm are the only children. ++ */ ++&spi0 { ++ compatible = "aspeed,ast2700-spi-txrx"; ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_spi0_default &pinctrl_spi0_cs1_default>; ++ /delete-node/ flash@0; ++ /delete-node/ flash@1; ++ spidev@0 { ++ /* BIOS flash: CPLD (spi_chnl_select) selects which of two flashes */ ++ compatible = "rohm,dh2228fv"; ++ reg = <0>; ++ status = "okay"; ++ }; ++ /* TPM on chip select 1; both ST33 and Infineon SLB9672 use tpm_tis_spi */ ++ tpm@1 { ++ compatible = "st,st33htpm-spi", "infineon,slb9670", "tcg,tpm_tis-spi"; ++ reg = <1>; ++ spi-max-frequency = <10000000>; ++ /* ++ * NOTE: this property is NOT consumed by any driver. Stock ++ * tpm_tis_spi (and all other drivers matching the compatibles ++ * above) does not call gpiod_get() for this name. That is ++ * intentional -- the SPI/TPM level shifters are enabled by the ++ * gpio-hogs on exp0 (see below), not by this device. ++ * ++ * It is kept purely as an fw_devlink ordering hint: any property ++ * whose name ends in "-gpios" is parsed by the DT core to build ++ * a supplier/consumer link. The phandle to exp0 therefore makes ++ * exp0 a supplier of tpm@1, so tpm@1 is not probed until the ++ * pcal6524 has probed and its hogs have run. Without this hint ++ * there is no ordering between the i2c5 and spi0 buses, and the ++ * TPM could be accessed before the buffers are enabled (races to ++ * "no TPM found"). Do not delete it. ++ * ++ * The property name is deliberately a private one ++ * ("buf-en-link-gpios") that no upstream driver consumes. If ++ * the property were called "enable-gpios" and a future kernel ++ * added gpiod_get(dev, "enable", ...) to tpm_tis_spi, it would ++ * collide with the hogs and fail -EBUSY. ++ */ ++ buf-en-link-gpios = <&exp0 4 GPIO_ACTIVE_LOW>, ++ <&exp0 5 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++#if 0 ++&fmc { ++ status = "okay"; ++ pinctrl-0 = <&pinctrl_fwspi_quad_default>; ++ pinctrl-names = "default"; ++ ++ flash@0 { ++ status = "okay"; ++ m25p,fast-read; ++ label = "bmc"; ++ spi-max-frequency = <20000000>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ u-boot@0 { ++ reg = <0x0 0x300000>; // 3MB ++ label = "u-boot"; ++ }; ++ ++ /* TODO: move to eMMC */ ++ u-boot-env@300000 { ++ reg = <0x300000 0x20000>; // 128KB ++ label = "u-boot-env"; ++ }; ++ ++ kernel@320000 { ++ reg = <0x320000 0x900000>; // 9MB ++ label = "kernel"; ++ }; ++ rofs@c20000 { ++ reg = <0xc20000 0x3000000>; // 48MB ++ label = "rofs"; ++ }; ++ rwfs@3c20000 { ++ reg = <0x3C20000 0x3E0000>; // ~4MB ++ label = "rwfs"; ++ }; ++ }; ++ }; ++ ++ flash@1 { ++ status = "okay"; ++ m25p,fast-read; ++ label = "fmc0:1"; ++ spi-max-frequency = <20000000>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ }; ++ ++ flash@2 { ++ status = "disabled"; ++ m25p,fast-read; ++ label = "fmc0:2"; ++ spi-max-frequency = <20000000>; ++ spi-tx-bus-width = <4>; ++ spi-rx-bus-width = <4>; ++ }; ++}; ++#endif ++ ++&rtc { ++ status = "okay"; ++}; ++ ++&uart1 { ++ status = "okay"; ++}; ++ ++&uart12 { ++ // BMC Debug Console ++ status = "okay"; ++}; ++ ++&mdio0 { ++ status = "disabled"; ++}; ++ ++&mdio1 { ++ status = "disabled"; ++}; ++ ++&mac0 { ++ status = "disabled"; ++}; ++ ++&mac1 { ++ status = "disabled"; ++}; ++ ++&sgmii { ++ status = "okay"; ++ #phy-cells = <0>; ++}; ++ ++&mdio2 { ++ status = "okay"; ++ reset-gpios = <&exp0 10 GPIO_ACTIVE_LOW>; ++ reset-delay-us = <30000>; ++ reset-post-delay-us = <30000>; ++ ++ ethphy2: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ marvell,reg-init = <0 0x10 0xffff 0x3060>, ++ <3 0x10 0xF000 0x0117>, ++ <3 0x11 0x00C0 0x4405>; ++ }; ++}; ++ ++&mac2 { ++ status = "okay"; ++ phy-mode = "sgmii"; ++ phy-handle = <ðphy2>; ++ phys = <&sgmii>; ++ phy-names = "sgmii-phy"; ++}; ++ ++/* ++ * Enable port A as device (via the virtual hub) and port B as ++ * host by default on the eval board. This can be easily changed ++ * by replacing the override below with &ehci0 { ... } to enable ++ * host on both ports. ++ */ ++&vhuba0 { ++ status = "okay"; ++}; ++ ++/* USB PORT B - MCU and Power bank */ ++/* This is an assembly option */ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++}; ++ ++/* I2C bus connecting BMC to CPU for IPMI */ ++/* Note : On Chameleon SPC6 on 2600 it will be i2c-0, on 2700 i2c-16 */ ++&i2c1 { ++ status = "okay"; ++ bus-frequency = <100000>; /* 100 KHz standard mode */ ++ /* BMC as I2C slave for IPMB */ ++ ipmb@20 { ++ compatible = "ipmb-dev"; ++ reg = <0x20>; /* BMC slave address (7-bit) */ ++ slave-dev; /* This is a slave device */ ++ }; ++}; ++ ++ ++&i2c2 { ++ status = "disabled"; ++}; ++ ++&i2c3 { ++ status = "okay"; ++ bus-frequency = <100000>; /* 100 KHz */ ++ aspeed,hw-timeout-ms = <1000>; ++ multi-master; ++}; ++ ++&i2c4 { ++ status = "okay"; ++ ++ ext_rtc: rtc@6f { ++ compatible = "nxp,pcf85053a"; ++ reg = <0x6f>; ++ }; ++}; ++ ++&i2c5 { ++ status = "okay"; ++ exp0: pcal6524@20 { ++ status = "okay"; ++ compatible = "nxp,pcal6524"; ++ reg = <0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reset-gpios = <&gpio1 ASPEED_GPIO(S, 0) GPIO_ACTIVE_LOW>; /*GPIO_BMC_GPIO_EXP_RESET_L*/ ++ ++ gpio-line-names = ++ "RSRVD_0", "GP_EROT_RST_IN_L", ++ "GP_3V3_BMC_PHY_PG", "GP_BMC_PWR_CYCLE_3V3_MASK_L", ++ "GP_BMC_SPI_BUF_OE_L", "GP_BMC_SPI_TPM_BUF_OE_L", ++ "SE_CPLD_EROT_BOOT_COMPLETE", "GP_BMC_WP_CTRL_L", ++ "GP_BMC_REC_SPI_MUX1_SEL", "RSRVD_1", ++ "S_BMC_GPIO_PHY_RST_L", "GP_JTAG_BMC_CPLD_BURN_EN_L", ++ "GP_PWR_BANK_PRESENT_L", "RSRVD_2", ++ "RSRVD_3", "RSRVD_4", ++ "RSRVD_5", "RSRVD_6", ++ "RSRVD_7", "GP_PROD_CS_FLASH0_EN", ++ "RSRVD_8", "GP_PROD_CS_FLASH1_EN", ++ "RSRVD_9", "RSRVD_10"; ++ /* ++ * Enable the SPI/TPM level shifters at gpiochip registration, ++ * i.e. during this node's probe -- before tpm@1 (ordered after ++ * us via the buf-en-link-gpios phandle above) touches ++ * the bus. ++ * ++ * POLARITY: these nets are active-low (..._OE_L), so physical low ++ * enables the buffer. In a gpio-hog, output-low/output-high are ++ * LOGICAL values and are inverted by GPIO_ACTIVE_LOW. Therefore ++ * "output-high" = logical 1 = physical low = buffer ENABLED. ++ * Using "output-low" here would drive the pin high and DISABLE ++ * the buffers -- the opposite of what we want. ++ */ ++ spi-buf-oe { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_LOW>; /* GP_BMC_SPI_BUF_OE_L */ ++ output-high; /* -> physical low -> enabled */ ++ }; ++ ++ spi-tpm-buf-oe { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_LOW>; /* GP_BMC_SPI_TPM_BUF_OE_L */ ++ output-high; /* -> physical low -> enabled */ ++ }; ++ }; ++}; ++ ++&i2c6 { ++ status = "okay"; ++}; ++ ++&i2c7 { ++ status = "okay"; ++ clock-frequency = <400000>; ++ i2c-tck-thddat-config = <0x0099EC00>; ++}; ++ ++&i2c8 { ++ status = "okay"; ++ clock-frequency = <400000>; ++ i2c-tck-thddat-config = <0x0099EC00>; ++}; ++ ++/* Used by I3C */ ++&i2c9 { ++ status = "disabled"; ++}; ++ ++&i2c10 { ++ status = "okay"; ++ clock-frequency = <400000>; ++ i2c-tck-thddat-config = <0x0099EC00>; ++}; ++ ++&i2c11 { ++ status = "disabled"; ++}; ++ ++&i2c12 { ++ status = "disabled"; ++}; ++ ++/* CPU master to BMC slave recovery interface */ ++/* Note: On Chameleon SPC6 multi - on 2600 it will be i2c-9, on 2700 - i2c-13 */ ++&i2c13 { ++ status = "okay"; ++ clock-frequency = <400000>; ++ i2c-tck-thddat-config = <0x0099EC00>; ++ /* ++ * BMC slave device (slave-24c02 at 0x42) is to be instantiated via ++ * bmc-i2c-slave-setup.service at boot. This approach ensures the ++ * I2C_CLIENT_SLAVE flag (0x1042) is properly set, which is required ++ * for the Aspeed I2C controller to register the hardware slave address. ++ * ++ * DTS-based instantiation doesn't set the I2C_CLIENT_SLAVE flag, causing: ++ * "i2c_slave_register: client slave flag not set. You might see address collisions" ++ * and preventing proper slave address registration in hardware. ++ * ++ * Note: "multi-master" is not required. ++ * ++ * Manual instantiation: echo slave-24c02 0x1042 > /sys/bus/i2c/devices/i2c-9/new_device ++ * Consider to provide service: /etc/systemd/system/bmc-i2c-slave-setup.service ++ */ ++}; ++ ++&i2c14 { ++ status = "okay"; ++ cpld: nvsw_bmc_hid189@31 { ++ compatible = "nvidia,hid189"; ++ reg = <0x31>; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ }; ++}; ++ ++&i2c15 { ++ status = "okay"; ++}; ++ ++&pcie0 { ++ status = "okay"; ++}; ++ ++&mctp0 { ++ status = "okay"; ++}; ++ ++&jtag0 { ++ status = "okay"; ++}; ++ ++&jtag1 { ++ status = "okay"; ++}; ++ ++// Enable emmc ++&emmc_controller { ++ status = "okay"; ++ mmc-hs200-1_8v; ++}; ++ ++&emmc { ++ status = "okay"; ++ non-removable; ++ bus-width = <4>; ++ max-frequency = <52000000>; ++}; ++ ++/* eSPI Controller - Communication with host CPU */ ++&espi0 { ++ status = "okay"; ++ perif-dma-mode; ++ perif-mmbi-enable; ++ perif-mmbi-src-addr = <0x0 0xa8000000>; ++ perif-mmbi-tgt-memory = <&espi0_mmbi_memory>; ++ perif-mmbi-instance-num = <0x1>; ++ perif-mcyc-enable; ++ perif-mcyc-src-addr = <0x0 0x98000000>; ++ perif-mcyc-size = <0x0 0x10000>; ++ oob-dma-mode; ++ flash-dma-mode; ++}; ++ ++// TODO: FIXME probably N/A for in 2700 ++#if 0 ++&lpc_ctrl { ++ status = "okay"; ++ memory-region = <&espi_memory>; ++}; ++ ++&lpc_reset { ++ status = "okay"; ++}; ++#endif ++ ++/* ++ * LPC SNOOP for POST code capture (simpler alternative to PCC) ++ * ++ * SNOOP driver benefits: ++ * - Mainline Linux driver (well-tested, stable) ++ * - Two independent channels for monitoring multiple ports ++ * - Simple FIFO-based interface via /dev/aspeed-lpc-snoop0/1 ++ * ++ * Usage: ++ * modprobe aspeed-lpc-snoop ++ * hexdump -C /dev/aspeed-lpc-snoop0 # Monitor port 0x80 ++ * hexdump -C /dev/aspeed-lpc-snoop1 # Monitor port 0x81 (if configured) ++ */ ++&pcie_lpc0_snoop { ++ status = "okay"; ++ snoop-ports = <0x80>; /* Capture POST codes from port 0x80 */ ++ /* ++ * Optional: Add second port for dual-channel monitoring ++ * snoop-ports = <0x80>, <0x81>; ++ */ ++}; ++ ++/* ++ * PCC disabled - cannot run simultaneously with SNOOP ++ * (both use same hardware registers: SNPWADR, HICR5, HICR6) ++ */ ++&pcie_lpc0_pcc { ++ status = "disabled"; ++}; ++ ++&pcie_lpc0_kcs0 { ++ status = "okay"; ++ kcs-io-addr = <0x3a0>; ++ kcs-channel = <1>; ++}; ++ ++&pcie_lpc0_kcs1 { ++ status = "okay"; ++ kcs-io-addr = <0x3a8>; ++ kcs-channel = <2>; ++}; ++ ++&pcie_lpc0_kcs2 { ++ status = "okay"; ++ /* Primary IPMI interface */ ++ kcs-io-addr = <0x3a2>; ++ kcs-channel = <3>; ++}; ++ ++&pcie_lpc0_kcs3 { ++ status = "disabled"; ++}; ++ ++// TODO: FIXME ++#if 0 ++&pinctrl0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_espi0_default>, ++ <&pinctrl_espialt_default>; pinctrl_salt0_default ???? ++}; ++#endif ++ ++/* ++ * I3C Controller for MCTP communication ++ * Note: pinctrl is already configured in aspeed-g7.dtsi base DTS ++ */ ++&i3c1 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ i3c-scl-hz = <12500000>; ++ internal-pullup = <1>; ++ mctp-controller; ++}; +diff --git a/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc.dts b/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc.dts +index b16c766ec..3cdda09d7 100644 +--- a/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc.dts ++++ b/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc.dts +@@ -5,7 +5,7 @@ + #include + #include + #include +-#include "nvidia-ast27xx-sunda.dtsi" ++#include "nvidia-ast27xx-sunda-sonic.dtsi" + + #define PCIE0_EP 1 // 1: EP, 0: RC + +diff --git a/arch/arm64/boot/dts/aspeed/nvidia-ast27xx-irot-sonic.dtsi b/arch/arm64/boot/dts/aspeed/nvidia-ast27xx-irot-sonic.dtsi +new file mode 100644 +index 000000000..650a72359 +--- /dev/null ++++ b/arch/arm64/boot/dts/aspeed/nvidia-ast27xx-irot-sonic.dtsi +@@ -0,0 +1,14 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++/ { ++ mctpirot0 { ++ compatible = "nvidia,ast27xx,irot"; ++ mboxes = <&mbox0 0>; ++ mbox-names = "irot"; ++ status = "okay"; ++ }; ++}; ++ ++&mbox0 { ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/aspeed/nvidia-ast27xx-sunda-sonic.dtsi b/arch/arm64/boot/dts/aspeed/nvidia-ast27xx-sunda-sonic.dtsi +new file mode 100644 +index 000000000..db26b5096 +--- /dev/null ++++ b/arch/arm64/boot/dts/aspeed/nvidia-ast27xx-sunda-sonic.dtsi +@@ -0,0 +1,8 @@ ++#include "nvidia-ast27xx-irot-sonic.dtsi" ++// OP-TEE vROT not used on SONiC BMC; same as meta nvidia-ast27xx-sunda.dtsi. ++//#include "nvidia-optee-vrot.dtsi" ++ ++// Enable OTP; matches OpenBMC AST2700 sund stack (DTS node + ast2700_otp.cfg). ++&otp { ++ status = "okay"; ++}; +-- +2.34.1 + diff --git a/patches-sonic/0010-net-ftgmac100-hard-reset-mac-for-sgmii.patch b/patches-sonic/0010-net-ftgmac100-hard-reset-mac-for-sgmii.patch new file mode 100644 index 0000000..1c79fad --- /dev/null +++ b/patches-sonic/0010-net-ftgmac100-hard-reset-mac-for-sgmii.patch @@ -0,0 +1,48 @@ +From: Sergejs Hatinecs +Date: Thu, 12 Jun 2026 12:00:00 +0300 +Subject: [PATCH 6.12 1/1] net: ftgmac100: hard-reset MAC for SGMII to clear RX stall + +Upstream-Status: Pending + +On AST2700 + Marvell 88E151x over SGMII, an "ifconfig down/up" (or a +partner-side link flap) intermittently leaves the MAC receive path wedged: +the link comes back up and reports resolved, TX works, but RX stays frozen +(no DHCP, no ping). The MDIO/serdes registers look identical to a healthy +link in this state, so the wedge is below the register layer. + +The only reliable recovery is "modprobe -r ftgmac100 / modprobe ftgmac100", +which re-runs probe and performs a full reset_control cycle of the MAC IP +block. The ndo_open/ftgmac100_reset() path only issues the soft MACCR reset, +which does not clear the wedged RX path. + +ftgmac100_reset_and_config_mac() already does the reset_control assert/ +deassert for RMII; extend it to SGMII so every MAC reset hard-resets the IP +block and clears the RX path, matching the modprobe-reload behaviour. With +this, repeated down/up cycles and partner link flaps recover reliably. + +Signed-off-by: Sergejs Hatinecs +--- + drivers/net/ethernet/faraday/ftgmac100.c | 12 +++++++++--- + 1 file changed, 9 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/drivers/net/ethernet/faraday/ftgmac100.c +index 8ef2b736f23e..a3534b467aa6 100644 +--- a/drivers/net/ethernet/faraday/ftgmac100.c ++++ b/drivers/net/ethernet/faraday/ftgmac100.c +@@ -157,8 +157,14 @@ static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv) + { + u32 maccr = 0; + +- /* RMII needs SCU reset to clear status */ +- if (priv->netdev->phydev->interface == PHY_INTERFACE_MODE_RMII) { ++ /* RMII needs SCU reset to clear status. SGMII (AST2700 + 88E151x) needs ++ * it too: after ifconfig down/up the soft MACCR reset alone leaves the ++ * MAC RX path wedged (link reads resolved but RX stays frozen). Only a ++ * full reset_control cycle clears it - this is why "modprobe -r/modprobe" ++ * (which hard-resets at probe) always recovers while down/up does not. ++ */ ++ if (priv->netdev->phydev->interface == PHY_INTERFACE_MODE_RMII || ++ priv->netdev->phydev->interface == PHY_INTERFACE_MODE_SGMII) { + int err; + + err = reset_control_assert(priv->rst); diff --git a/patches-sonic/0011-arm64-dts-aspeed-spc6-bmc-fix-sgmii-phy-names.patch b/patches-sonic/0011-arm64-dts-aspeed-spc6-bmc-fix-sgmii-phy-names.patch new file mode 100644 index 0000000..09219ec --- /dev/null +++ b/patches-sonic/0011-arm64-dts-aspeed-spc6-bmc-fix-sgmii-phy-names.patch @@ -0,0 +1,60 @@ +From: Sergejs Hatinecs +Date: Thu, 12 Jun 2026 12:30:00 +0300 +Subject: [PATCH 6.12 1/1] arm64: dts: aspeed: spc6-bmc: fix mac2 SGMII phy-names + +Upstream-Status: Pending + +ftgmac100 probes the optional SGMII serdes PHY with devm_phy_optional_get() +using the name "sgmii". mac2 in the SPC6 BMC device trees used +phy-names = "sgmii-phy", so the serdes PHY was never bound and SGMII +management traffic did not run through the expected path. + +Use phy-names = "sgmii" on mac2 in the A1, SONiC, and OpenBMC SPC6 BMC +DTS variants so the name matches the driver. + +Signed-off-by: Sergejs Hatinecs +--- + arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-a1-bmc.dts | 2 +- + arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc-openbmc.dts | 2 +- + arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc.dts | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-a1-bmc.dts b/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-a1-bmc.dts +index 810d50fe11ac..741bd588ec2a 100644 +--- a/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-a1-bmc.dts ++++ b/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-a1-bmc.dts +@@ -170,7 +170,7 @@ + phy-mode = "sgmii"; + phy-handle = <ðphy2>; + phys = <&sgmii>; +- phy-names = "sgmii-phy"; ++ phy-names = "sgmii"; + }; + + /* +diff --git a/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc.dts b/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc.dts +index 0817034b8658..e16559039ed5 100644 +--- a/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc.dts ++++ b/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc.dts +@@ -207,7 +207,7 @@ + phy-mode = "sgmii"; + phy-handle = <ðphy2>; + phys = <&sgmii>; +- phy-names = "sgmii-phy"; ++ phy-names = "sgmii"; + }; + + /* +diff --git a/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc-openbmc.dts b/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc-openbmc.dts +index cfe5743b90fe..bcdb5a463b42 100644 +--- a/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc-openbmc.dts ++++ b/arch/arm64/boot/dts/aspeed/aspeed-nvidia-spc6-bmc-openbmc.dts +@@ -215,7 +215,7 @@ + phy-mode = "sgmii"; + phy-handle = <ðphy2>; + phys = <&sgmii>; +- phy-names = "sgmii-phy"; ++ phy-names = "sgmii"; + }; + + /* diff --git a/patches-sonic/0012-usb-ehci-Add-Aspeed-AST2700-support.patch b/patches-sonic/0012-usb-ehci-Add-Aspeed-AST2700-support.patch new file mode 100644 index 0000000..432f1a5 --- /dev/null +++ b/patches-sonic/0012-usb-ehci-Add-Aspeed-AST2700-support.patch @@ -0,0 +1,79 @@ +From: Ryan Chen +Date: Sun, 28 Sep 2025 03:24:07 +0000 +Subject: [PATCH 6.12 1/1] usb: ehci: Add Aspeed AST2700 support + +Upstream-Status: Backport [274f2232a94f6ca626d60288044e13d9a58c7612] + +Unlike earlier Aspeed SoCs (AST2400/2500/2600) which are limited to +32-bit DMA addressing, the EHCI controller in AST2700 supports 64-bit +DMA. Update the EHCI platform driver to make use of this capability by +selecting a 64-bit DMA mask when the "aspeed,ast2700-ehci" compatible +is present in device tree. + +Without this, ehci-platform probe of usb@12063000 (EHCI1, USB Port B) +on SPC6 AST2700 BMC fails with -ENOMEM when DTS enables &ehci1. + +Signed-off-by: Ryan Chen +Reviewed-by: Alan Stern +--- + drivers/usb/host/ehci-platform.c | 15 +++++++++++++-- + 1 file changed, 13 insertions(+), 2 deletions(-) + +diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c +index cdf41886e8ca..dd6a93edf4de 100644 +--- a/drivers/usb/host/ehci-platform.c ++++ b/drivers/usb/host/ehci-platform.c +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -238,9 +239,11 @@ static int ehci_platform_probe(struct platform_device *dev) + struct usb_hcd *hcd; + struct resource *res_mem; + struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev); ++ const struct of_device_id *match; + struct ehci_platform_priv *priv; + struct ehci_hcd *ehci; + int err, irq, clk = 0; ++ bool dma_mask_64; + + if (usb_disabled()) + return -ENODEV; +@@ -252,8 +255,13 @@ static int ehci_platform_probe(struct platform_device *dev) + if (!pdata) + pdata = &ehci_platform_defaults; + ++ dma_mask_64 = pdata->dma_mask_64; ++ match = of_match_device(dev->dev.driver->of_match_table, &dev->dev); ++ if (match && match->data) ++ dma_mask_64 = true; ++ + err = dma_coerce_mask_and_coherent(&dev->dev, +- pdata->dma_mask_64 ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32)); ++ dma_mask_64 ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32)); + if (err) { + dev_err(&dev->dev, "Error: DMA mask configuration failed\n"); + return err; +@@ -297,7 +305,9 @@ static int ehci_platform_probe(struct platform_device *dev) + if (of_device_is_compatible(dev->dev.of_node, + "aspeed,ast2500-ehci") || + of_device_is_compatible(dev->dev.of_node, +- "aspeed,ast2600-ehci")) ++ "aspeed,ast2600-ehci") || ++ of_device_is_compatible(dev->dev.of_node, ++ "aspeed,ast2700-ehci")) + ehci->is_aspeed = 1; + + if (soc_device_match(quirk_poll_match)) +@@ -484,6 +494,7 @@ static const struct of_device_id vt8500_ehci_ids[] = { + { .compatible = "wm,prizm-ehci", }, + { .compatible = "generic-ehci", }, + { .compatible = "cavium,octeon-6335-ehci", }, ++ { .compatible = "aspeed,ast2700-ehci", .data = (void *)1 }, + {} + }; + MODULE_DEVICE_TABLE(of, vt8500_ehci_ids); diff --git a/patches-sonic/0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch b/patches-sonic/0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch index ac814fd..d456349 100644 --- a/patches-sonic/0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch +++ b/patches-sonic/0046-platform-mellanox-nvsw-bmc-Add-system-control-and-mo.patch @@ -1,4 +1,4 @@ -From ac19027ee711c9ab109c8cacde22af73483179db Mon Sep 17 00:00:00 2001 +From 79d11ae9b4611ac726289d9a27f4ac065c6a0efc Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Thu, 4 Jul 2024 23:50:27 +0300 Subject: [PATCH BMC platform-next 1/4] platform/mellanox: nvsw-bmc: Add system @@ -23,13 +23,13 @@ Signed-off-by: Vadim Pasternak .../devicetree/bindings/trivial-devices.yaml | 5 + drivers/platform/mellanox/Kconfig | 38 + drivers/platform/mellanox/Makefile | 4 + - drivers/platform/mellanox/nvsw-bmc-hid162.c | 7285 +++++++++++++++++ + drivers/platform/mellanox/nvsw-bmc-hid162.c | 7304 +++++++++++++++++ drivers/platform/mellanox/nvsw-core.c | 717 ++ - drivers/platform/mellanox/nvsw-host-l1.c | 770 ++ + drivers/platform/mellanox/nvsw-host-l1.c | 735 ++ drivers/platform/mellanox/nvsw-host-spc5.c | 943 +++ drivers/platform/mellanox/nvsw-host-spc6.c | 852 ++ drivers/platform/mellanox/nvsw.h | 318 + - 9 files changed, 10932 insertions(+) + 9 files changed, 10916 insertions(+) create mode 100644 drivers/platform/mellanox/nvsw-bmc-hid162.c create mode 100644 drivers/platform/mellanox/nvsw-core.c create mode 100644 drivers/platform/mellanox/nvsw-host-l1.c @@ -106,7 +106,7 @@ diff --git a/drivers/platform/mellanox/Makefile b/drivers/platform/mellanox/Make index e86723b44c2e..123edaa99d77 100644 --- a/drivers/platform/mellanox/Makefile +++ b/drivers/platform/mellanox/Makefile -@@ -11,4 +11,8 @@ obj-$(CONFIG_MLXREG_DPU) += mlxreg-dpu.o +@@ -9,4 +9,8 @@ obj-$(CONFIG_MLXBF_TMFIFO) += mlxbf-tmfifo.o obj-$(CONFIG_MLXREG_HOTPLUG) += mlxreg-hotplug.o obj-$(CONFIG_MLXREG_IO) += mlxreg-io.o obj-$(CONFIG_MLXREG_LC) += mlxreg-lc.o @@ -117,10 +117,9 @@ index e86723b44c2e..123edaa99d77 100644 obj-$(CONFIG_NVSW_SN2201) += nvsw-sn2201.o diff --git a/drivers/platform/mellanox/nvsw-bmc-hid162.c b/drivers/platform/mellanox/nvsw-bmc-hid162.c new file mode 100644 -index 000000000000..89343d7660a4 --- /dev/null +++ b/drivers/platform/mellanox/nvsw-bmc-hid162.c -@@ -0,0 +1,7285 @@ +@@ -0,0 +1,7304 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Nvidia BMC platform driver @@ -374,6 +373,18 @@ index 000000000000..89343d7660a4 + +static struct mlxreg_core_data nvsw_bmc_hid191_events_items_data[] = { + { ++ .label = "holder6_pg", ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = NVSW_PWR_BUTTON_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { ++ .label = "holder7_pg", ++ .reg = NVSW_REG_PWRB_OFFSET, ++ .mask = NVSW_AMB_TEMP_SENSE_MASK, ++ .hpdev.nr = NVSW_NR_NONE, ++ }, ++ { + .label = "graceful_power_off_req", + .reg = NVSW_REG_PWRB_OFFSET, + .mask = NVSW_GRACEFUL_POWER_OFF_MASK, @@ -1348,7 +1359,7 @@ index 000000000000..89343d7660a4 + }, + { + .label = "thermtrip_alert", -+ .reg = NVSW_REG_BRD1_OFFSET, ++ .reg = NVSW_REG_HEALTH_OFFSET, + .mask = BIT(3), + .hpdev.nr = NVSW_NR_NONE, + }, @@ -1555,6 +1566,7 @@ index 000000000000..89343d7660a4 + .count = ARRAY_SIZE(nvsw_bmc_hid180_asic_temp_items_data), + .inversed = 0, + .health = false, ++ .non_sticky = true, + }, + { + .data = nvsw_bmc_hid180_leakage_items_data, @@ -2372,6 +2384,7 @@ index 000000000000..89343d7660a4 + .count = ARRAY_SIZE(nvsw_bmc_hid181_asic_temp_items_data), + .inversed = 0, + .health = false, ++ .non_sticky = true, + }, + { + .data = nvsw_bmc_hid181_leakage_items_data, @@ -2422,7 +2435,8 @@ index 000000000000..89343d7660a4 + .data = nvsw_bmc_hid181_events_items_data, + .aggr_mask = NVSW_AGGR_MASK, + .reg = NVSW_REG_PWRB_OFFSET, -+ .mask = NVSW_GRACEFUL_POWER_OFF_MASK | NVSW_CPU_POWER_OFF_READY_MASK | ++ .mask = NVSW_PWR_BUTTON_MASK | NVSW_AMB_TEMP_SENSE_MASK | ++ NVSW_GRACEFUL_POWER_OFF_MASK | NVSW_CPU_POWER_OFF_READY_MASK | + NVSW_CPU_RESET_MASK | NVSW_APML_SMB_ALERT_MASK | + NVSW_CPU_UNEXP_POWER_OFF_MASK, + .count = ARRAY_SIZE(nvsw_bmc_hid181_events_items_data), @@ -3065,7 +3079,7 @@ index 000000000000..89343d7660a4 + }, + { + .label = "thermtrip_alert", -+ .reg = NVSW_REG_BRD1_OFFSET, ++ .reg = NVSW_REG_HEALTH_OFFSET, + .mask = BIT(3), + .hpdev.nr = NVSW_NR_NONE, + }, @@ -3135,6 +3149,7 @@ index 000000000000..89343d7660a4 + .count = ARRAY_SIZE(nvsw_bmc_hid191_asic_temp_items_data), + .inversed = 0, + .health = false, ++ .non_sticky = true, + }, + { + .data = nvsw_bmc_hid191_vr1_pwr_alert_items_data, @@ -3214,7 +3229,8 @@ index 000000000000..89343d7660a4 + .data = nvsw_bmc_hid191_events_items_data, + .aggr_mask = NVSW_AGGR_MASK, + .reg = NVSW_REG_PWRB_OFFSET, -+ .mask = NVSW_GRACEFUL_POWER_OFF_MASK | NVSW_CPU_POWER_OFF_READY_MASK | ++ .mask = NVSW_PWR_BUTTON_MASK | NVSW_AMB_TEMP_SENSE_MASK | ++ NVSW_GRACEFUL_POWER_OFF_MASK | NVSW_CPU_POWER_OFF_READY_MASK | + NVSW_CPU_RESET_MASK | NVSW_APML_SMB_ALERT_MASK | + NVSW_CPU_UNEXP_POWER_OFF_MASK, + .count = ARRAY_SIZE(nvsw_bmc_hid191_events_items_data), @@ -3487,6 +3503,7 @@ index 000000000000..89343d7660a4 + .count = ARRAY_SIZE(nvsw_bmc_hid193_asic_temp_items_data), + .inversed = 0, + .health = false, ++ .non_sticky = true, + }, + { + .data = nvsw_bmc_hid193_dc_ok_events_items_data, @@ -3557,7 +3574,8 @@ index 000000000000..89343d7660a4 + .data = nvsw_bmc_hid191_events_items_data, + .aggr_mask = NVSW_AGGR_MASK, + .reg = NVSW_REG_PWRB_OFFSET, -+ .mask = NVSW_GRACEFUL_POWER_OFF_MASK | NVSW_CPU_POWER_OFF_READY_MASK | ++ .mask = NVSW_PWR_BUTTON_MASK | NVSW_AMB_TEMP_SENSE_MASK | ++ NVSW_GRACEFUL_POWER_OFF_MASK | NVSW_CPU_POWER_OFF_READY_MASK | + NVSW_CPU_RESET_MASK | NVSW_APML_SMB_ALERT_MASK | + NVSW_CPU_UNEXP_POWER_OFF_MASK, + .count = ARRAY_SIZE(nvsw_bmc_hid191_events_items_data), @@ -8131,15 +8149,15 @@ index 000000000000..1bd2dfc622ce +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/platform/mellanox/nvsw-host-l1.c b/drivers/platform/mellanox/nvsw-host-l1.c new file mode 100644 -index 000000000000..83d305080150 +index 000000000..6fb8cf07a --- /dev/null +++ b/drivers/platform/mellanox/nvsw-host-l1.c -@@ -0,0 +1,770 @@ +@@ -0,0 +1,735 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* -+ * Nvidia BMC platform driver ++ * Nvidia L1 host platform driver + * -+ * Copyright (C) 2025 Nvidia Technologies Ltd. ++ * Copyright (C) 2025-2026 Nvidia Technologies Ltd. + */ + +#include @@ -8182,9 +8200,9 @@ index 000000000000..83d305080150 +static const int nvsw_host_l1_mgmt_channels[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, + 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, -+ 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 48, 49, -+ 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, -+ 65, 66, 67, 68, 69, 70, 71, ++ 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, ++ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, ++ 63, 64, 65, 66, 67, +}; + +/* Platform L1 scale out mux data */ @@ -8392,12 +8410,6 @@ index 000000000000..83d305080150 + .mode = 0444, + }, + { -+ .label = "cartridge_status_clear", -+ .reg = NVSW_REG_FRU1_EVENT_OFFSET, -+ .bit = GENMASK(3, 0), -+ .mode = 0644, -+ }, -+ { + .label = "leakage1", + .reg = NVSW_REG_LEAK_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), @@ -8410,12 +8422,6 @@ index 000000000000..83d305080150 + .mode = 0444, + }, + { -+ .label = "leakage_status_clear", -+ .reg = NVSW_REG_LEAK_EVENT_OFFSET, -+ .bit = GENMASK(1, 0), -+ .mode = 0644, -+ }, -+ { + .label = "asic_reset", + .reg = NVSW_REG_RESET_GP2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), @@ -8428,6 +8434,24 @@ index 000000000000..83d305080150 + .mode = 0644, + }, + { ++ .label = "cpu_erot_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mode = 0644, ++ }, ++ { ++ .label = "mcu1_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(6), ++ .mode = 0644, ++ }, ++ { ++ .label = "mcu2_reset", ++ .reg = NVSW_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0644, ++ }, ++ { + .label = "reset_long_pb", + .reg = NVSW_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(0), @@ -8440,7 +8464,7 @@ index 000000000000..83d305080150 + .mode = 0444, + }, + { -+ .label = "reset_aux_pwr_or_fu", ++ .label = "reset_aux_pwr_or_reload", + .reg = NVSW_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, @@ -8452,7 +8476,13 @@ index 000000000000..83d305080150 + .mode = 0444, + }, + { -+ .label = "reset_pwr_button_or_leak_con", ++ .label = "reset_platform", ++ .reg = NVSW_REG_RESET_CAUSE_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0444, ++ }, ++ { ++ .label = "reset_pwr_button", + .reg = NVSW_REG_RESET_CAUSE_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, @@ -8470,21 +8500,21 @@ index 000000000000..83d305080150 + .mode = 0444, + }, + { -+ .label = "reset_comex_pwr_fail", ++ .label = "reset_soc", + .reg = NVSW_REG_RESET_CAUSE1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mask = GENMASK(7, 0) & ~BIT(5), + .mode = 0444, + }, + { -+ .label = "reset_platform", ++ .label = "reset_cpu_erot", + .reg = NVSW_REG_RESET_CAUSE1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mask = GENMASK(7, 0) & ~BIT(6), + .mode = 0444, + }, + { -+ .label = "reset_soc", ++ .label = "reset_leak_con", + .reg = NVSW_REG_RESET_CAUSE1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), ++ .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, + }, + { @@ -8500,18 +8530,12 @@ index 000000000000..83d305080150 + .mode = 0444, + }, + { -+ .label = "reset_comex_thermal", ++ .label = "reset_cpu_thermal", + .reg = NVSW_REG_RESET_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0444, + }, + { -+ .label = "reset_comex_power", -+ .reg = NVSW_REG_RESET_CAUSE2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(4), -+ .mode = 0444, -+ }, -+ { + .label = "reset_pwr_converter_fail", + .reg = NVSW_REG_RESET_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(5), @@ -8524,7 +8548,7 @@ index 000000000000..83d305080150 + .mode = 0444, + }, + { -+ .label = "reset_mgmt_pwr", ++ .label = "reset_mgmt_pwr_fail", + .reg = NVSW_REG_RESET_CAUSE2_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(7), + .mode = 0444, @@ -8591,53 +8615,11 @@ index 000000000000..83d305080150 + .mode = 0644, + }, + { -+ .label = "config1", -+ .reg = NVSW_REG_CONFIG1_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+ { -+ .label = "config2", -+ .reg = NVSW_REG_CONFIG2_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+ { -+ .label = "config3", -+ .reg = NVSW_REG_CONFIG3_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, -+ { -+ .label = "sgmii_phy", -+ .reg = NVSW_REG_BRD1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0444, -+ }, -+ { -+ .label = "graseful_pwr_off", ++ .label = "graceful_pwr_off", + .reg = NVSW_REG_GP7_OFFSET, + .mask = GENMASK(7, 0) & ~BIT(3), + .mode = 0644, + }, -+ { -+ .label = "power_button_evt", -+ .reg = NVSW_REG_PWRB_EVENT_OFFSET, -+ .mask = GENMASK(7, 0) & ~NVSW_PWR_BUTTON_MASK, -+ .mode = 0644, -+ }, -+ { -+ .label = "power_button_mask", -+ .reg = NVSW_REG_PWRB_MASK_OFFSET, -+ .mask = GENMASK(7, 0) & ~NVSW_PWR_BUTTON_MASK, -+ .mode = 0644, -+ }, -+ { -+ .label = "amb_sens", -+ .reg = NVSW_REG_PWRB_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(1), -+ .mode = 0444, -+ }, +}; + +static struct mlxreg_core_platform_data nvsw_host_l1_regs_io = { @@ -8905,6 +8887,7 @@ index 000000000000..83d305080150 +MODULE_AUTHOR("Vadim Pasternak "); +MODULE_DESCRIPTION("Nvidia platform driver"); +MODULE_LICENSE("Dual BSD/GPL"); ++ diff --git a/drivers/platform/mellanox/nvsw-host-spc5.c b/drivers/platform/mellanox/nvsw-host-spc5.c new file mode 100644 index 000000000000..e54bd4109b79 @@ -11038,4 +11021,3 @@ index 000000000000..4fa0d9d31bdd + -- 2.34.1 - diff --git a/patches-sonic/0064-hwmon-pmbus-isl68137-Add-support-for-Renesas-RAA2289.patch b/patches-sonic/0064-hwmon-pmbus-isl68137-Add-support-for-Renesas-RAA2289.patch new file mode 100644 index 0000000..5146195 --- /dev/null +++ b/patches-sonic/0064-hwmon-pmbus-isl68137-Add-support-for-Renesas-RAA2289.patch @@ -0,0 +1,66 @@ +From cc38b3dd3d977941a93831f44cd0326a8e8ab34b Mon Sep 17 00:00:00 2001 +From: Vasily Vityukov +Date: Mon, 20 Apr 2026 12:19:20 +0300 +Subject: [PATCH] hwmon: pmbus/isl68137: Add support for Renesas RAA228942 and + RAA228943 + +Add I2C device IDs for Renesas RAA228942 and RAA228943. + +At the Linux PMBus hwmon interface level currently supported by this +driver, these devices are compatible with the existing 2-rail non-TC +controllers, so devicetree will use fallback compatibles and no +dedicated OF match entries are needed. + +Signed-off-by: Dawei Liu +--- + Documentation/hwmon/isl68137.rst | 20 ++++++++++++++++++++ + drivers/hwmon/pmbus/isl68137.c | 2 ++ + 2 files changed, 22 insertions(+) + +diff --git a/Documentation/hwmon/isl68137.rst b/Documentation/hwmon/isl68137.rst +index 0e71b22047f8..1a1424dd640f 100644 +--- a/Documentation/hwmon/isl68137.rst ++++ b/Documentation/hwmon/isl68137.rst +@@ -374,6 +374,26 @@ Supported chips: + + Publicly available (after August 2020 launch) at the Renesas website + ++ * Renesas RAA228942 ++ ++ Prefix: 'raa228942' ++ ++ Addresses scanned: - ++ ++ Datasheet: ++ ++ Provided by Renesas upon request and NDA ++ ++ * Renesas RAA228943 ++ ++ Prefix: 'raa228943' ++ ++ Addresses scanned: - ++ ++ Datasheet: ++ ++ Provided by Renesas upon request and NDA ++ + * Renesas RAA229001 + + Prefix: 'raa229001' +diff --git a/drivers/hwmon/pmbus/isl68137.c b/drivers/hwmon/pmbus/isl68137.c +index 7e53fb1d5ea3..f3baaee6227a 100644 +--- a/drivers/hwmon/pmbus/isl68137.c ++++ b/drivers/hwmon/pmbus/isl68137.c +@@ -311,6 +311,8 @@ static const struct i2c_device_id raa_dmpvr_id[] = { + {"raa228004", raa_dmpvr2_hv}, + {"raa228006", raa_dmpvr2_hv}, + {"raa228228", raa_dmpvr2_2rail_nontc}, ++ {"raa228942", raa_dmpvr2_2rail_nontc}, ++ {"raa228943", raa_dmpvr2_2rail_nontc}, + {"raa229001", raa_dmpvr2_2rail}, + {"raa229004", raa_dmpvr2_2rail}, + {} +-- +2.34.1 + diff --git a/patches-sonic/8014-mlxsw-i2c-Downstream-Increase-I2C-timeout-for-HW-sem.patch b/patches-sonic/8014-mlxsw-i2c-Downstream-Increase-I2C-timeout-for-HW-sem.patch new file mode 100644 index 0000000..2411f3d --- /dev/null +++ b/patches-sonic/8014-mlxsw-i2c-Downstream-Increase-I2C-timeout-for-HW-sem.patch @@ -0,0 +1,36 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nadav Hugi +Date: Mon, 25 May 2026 16:52:00 +0300 +Subject: [PATCH v6.12 1/1] mlxsw: i2c: Downstream: Increase I2C timeout for + HW semaphore stability + +When taking an IR core dump on SPC1 debug kernel, the firmware halts +its IRISCs to capture a clean snapshot. This pause takes ~5 seconds +and occasionally exceeds the driver's hardcoded 5-second I2C timeout, +causing spurious "HW semaphore is not released" errors. The system +recovers normally after the dump completes — this is not a real +hardware failure. + +Increase MLXSW_I2C_TIMEOUT_MSECS from 5000 to 10000 to give the +driver enough headroom to wait out the firmware pause. + +Signed-off-by: Nadav Hugi +--- + drivers/net/ethernet/mellanox/mlxsw/i2c.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/mellanox/mlxsw/i2c.c b/drivers/net/ethernet/mellanox/mlxsw/i2c.c +index XXXXXXX..YYYYYYY 100644 +--- a/drivers/net/ethernet/mellanox/mlxsw/i2c.c ++++ b/drivers/net/ethernet/mellanox/mlxsw/i2c.c +@@ -50,7 +50,7 @@ + #define MLXSW_I2C_BLK_DEF 32 + #define MLXSW_I2C_BLK_MAX 100 + #define MLXSW_I2C_RETRY 5 +-#define MLXSW_I2C_TIMEOUT_MSECS 5000 ++#define MLXSW_I2C_TIMEOUT_MSECS 10000 + #define MLXSW_I2C_CMD_RETRY_FW_ERR 3 + #define MLXSW_I2C_MAX_DATA_SIZE 256 + +-- +2.20.1 diff --git a/patches-sonic/series b/patches-sonic/series index fdb7d30..4dd01bb 100644 --- a/patches-sonic/series +++ b/patches-sonic/series @@ -65,7 +65,6 @@ driver-i2c-smbus-add-disable_spd-module-parameter.patch ###-> mellanox_sdk-end ###-> mellanox_hw_mgmt-start -0001-mlxbf-bootctl-Constify-struct-bin_attribute.patch 0002-platform-mellanox-mlxbf-pmc-Add-support-for-monitori.patch 0003-platform-mellanox-mlxbf-pmc-Add-support-for-clock_me.patch 0004-platform-mellanox-mlxbf-bootctl-use-sysfs_emit-inste.patch @@ -124,6 +123,7 @@ driver-i2c-smbus-add-disable_spd-module-parameter.patch 0061-platform-mellanox-mlxreg-io-Increase-max-supported-a.patch 0062-Add-support-for-NXP-s-PCF85053A-RTC-chip.patch 0063-reset-phy-using-polling-function-not-register-write.patch +0064-hwmon-pmbus-isl68137-Add-support-for-Renesas-RAA2289.patch 8000-mlxsw-Use-weak-reverse-dependencies-for-firmware-fla.patch 8002-mlxsw-i2c-SONIC-ISSU-Prevent-transaction-execution-f.patch 8003-mlxsw-minimal-Downstream-Ignore-error-reading-SPAD-r.patch @@ -136,6 +136,7 @@ driver-i2c-smbus-add-disable_spd-module-parameter.patch 8010-mlxsw-minimal-Downstream-Disable-ethtool-interface.patch 8011-hwmon-pmbus-Downstream-Workaround-for-psu-attributes.patch 8013-hwmon-pmbus-mp2975-Clear-interrupts-at-probe.patch +8014-mlxsw-i2c-Downstream-Increase-I2C-timeout-for-HW-sem.patch ###-> mellanox_hw_mgmt-end # Cisco patches for 5.10 kernel @@ -248,7 +249,6 @@ driver-tty-serial-8250-add-support-for-fintek-F81214E.patch # Linux upstream pen 0011-PCI-AER-Fix-NULL-pointer-access-by-aer_info.patch 0012-PCI-AER-Avoid-NULL-pointer-dereference-in-aer_rateli.patch - # QID-45097: Crackarmor fixes qsa-2026-apparmor/0001-apparmor-validate-DFA-start-states-are-in-bounds-in-.patch qsa-2026-apparmor/0002-apparmor-fix-memory-leak-in-verify_header.patch @@ -294,6 +294,11 @@ micas-m2-w6950-128oc-dts.patch 0005-mctp-driver-net-Fix-MCTP-over-USB.patch 0006-jtag-Add-JTAG-core-headers-GPIO-mux-and-locking-support.patch 0007-JTAG-Aspeed-Fix-kernel-configuration.patch +0008-arm64-dts-aspeed-spc6-bmc-ext-phram-env-tpm-i3c-pull.patch +0009-arm64-dts-aspeed-split-SPC6-BMC-DTS-for-SONiC-and-Op.patch +0010-net-ftgmac100-hard-reset-mac-for-sgmii.patch +0011-arm64-dts-aspeed-spc6-bmc-fix-sgmii-phy-names.patch +0012-usb-ehci-Add-Aspeed-AST2700-support.patch ###-> nvidia_aspeed_bmc-end #