Original project: https://www.edaplayground.com/x/ZzcD, titled CADENCE_YAPP_PACKET(2).
This is a portfolio presentation of my YAPP/UVM learning and integration exercise. The repository includes Cadence training/reference sources, with their existing notices retained. Many files cite the Cadence SystemVerilog Advanced/Accelerated Verification with UVM training and Copyright Cadence Design Systems (c)2015. The router header names Kathleen Meade, Brian Dickinson, and Lisa Barbay.
The portfolio smoke test, alternate compilation top, run/log-check scripts, and project documentation were added when preparing this repository. channel_rx_driver.sv also contains the documented receive-flow-control correction. These additions should be distinguished from the supplied reference RTL and UVC scaffolding.
No blanket open-source license is applied to the repository. Existing third-party copyright and usage terms remain applicable; public visibility does not grant additional redistribution rights.