From 47ca96a463bc5b47965eba6fc8144e37a284e532 Mon Sep 17 00:00:00 2001
From: Flavien Solt <flavien@nus.edu.sg>
Date: Thu, 13 Aug 2026 23:31:01 +0800
Subject: [PATCH] Fix DMA AXI address handshakes

---
 tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_read_engine.sv  | 5 +++--
 tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv | 4 ++--
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_read_engine.sv b/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_read_engine.sv
index 4854288..e9ad1db 100644
--- a/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_read_engine.sv
+++ b/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_read_engine.sv
@@ -91,13 +91,14 @@ module dma_read_engine #(
          end 
 
          state[ADDR_SETUP_BIT]:
-            if (src_mem.arready & ((rd_req_cnt-rlast_cnt)<NUM_PENDING_RDS))
+            if ((rd_req_cnt-rlast_cnt)<NUM_PENDING_RDS)
                next = SEND_RD_REQ; 
             else 
                next = ADDR_SETUP;
 
          state[SEND_RD_REQ_BIT]:
-            if ((rd_req_cnt+1) < num_rd_reqs) next = ADDR_SETUP; 
+            if (!src_mem.arready) next = SEND_RD_REQ;
+            else if ((rd_req_cnt+1) < num_rd_reqs) next = ADDR_SETUP;
             else if ((rd_req_cnt+1) >= num_rd_reqs) next = CP_RSP_TO_FIFO;
             else next = SEND_RD_REQ;
 
diff --git a/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv b/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv
index 1e4b558..313f13b 100644
--- a/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv
+++ b/tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv
@@ -96,7 +96,7 @@ module dma_write_engine #(
       next = XXX;
       unique case (1'b1)
          state[IDLE_BIT]: begin 
-           if (descriptor.descriptor_control.go & descriptor_fifo_not_empty & dest_mem.awready & rd_fifo_if.not_empty)next = SEND_WR_REQ;
+           if (descriptor.descriptor_control.go & descriptor_fifo_not_empty & rd_fifo_if.not_empty) next = SEND_WR_REQ;
            else next = IDLE;
          end 
 
@@ -275,7 +275,7 @@ module dma_write_engine #(
          end
 
          state[SEND_WR_REQ_BIT]:begin
-            dest_mem.awvalid = dest_mem.awready;
+            dest_mem.awvalid = 1'b1;
             rd_fifo_if.rd_en = 1'b0;
             dest_mem_wvalid  = 1'b0;
          end