SDRAM_controller.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:18:30 10/26/2023 
-- Design Name: 
-- Module Name:    SDRAM_controller - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SDRAM_controller is
    Port ( ADDR : in  STD_LOGIC_VECTOR (15 downto 0);
           WR_RD : in  STD_LOGIC;
           MSTRB : in  STD_LOGIC;
           Din : in  STD_LOGIC_VECTOR (7 downto 0);
           Dout : out  STD_LOGIC_VECTOR (7 downto 0);
           clk : in  STD_LOGIC);
end SDRAM_controller;

architecture Behavioral of SDRAM_controller is

type memory is array (65535 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
signal sdram_mem: memory := ((others=> (others=>'0')));

begin
	process(clk, MSTRB)
	begin
		if (clk'event AND clk = '1' AND MSTRB = '1') then
			if (WR_RD = '0') then
				Dout <= sdram_mem(to_integer(unsigned(ADDR)));
			elsif (WR_RD = '1') then
				sdram_mem(to_integer(unsigned(ADDR))) <= Din;
			end if;
		end if; 
	end process;
end Behavioral;