HardwareFinal/calculator_map.map at master · meatybobby/HardwareFinal · GitHub

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Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'calculator'

Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o calculator_map.ncd calculator.ngd calculator.pcf
Target Device  : xc6slx16
Target Package : csg324
Target Speed   : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date    : Sat Jun 27 19:01:54 2015

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 4 secs
Total CPU  time at the beginning of Placer: 4 secs

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:806c85bb) REAL time: 4 secs

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:806c85bb) REAL time: 4 secs

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:806c85bb) REAL time: 4 secs

Phase 4.2  Initial Placement for Architecture Specific Features

......
WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
   IOB component <rst> is placed at site <N3>. The corresponding BUFG component
   <rst_IBUF_BUFG> is placed at site <BUFGMUX_X3Y7>. There is only a select set
   of IOBs that can use the fast path to the Clocker buffer, and they are not
   being used. You may want to analyze why this problem exists and correct it.
   This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was
   applied on COMP.PIN <rst.PAD> allowing your design to continue. This
   constraint disables all clock placer rules related to the specified COMP.PIN.
   The use of this override is highly discouraged as it may lead to very poor
   timing results. It is recommended that this error condition be corrected in
   the design.
Phase 4.2  Initial Placement for Architecture Specific Features
(Checksum:4629010b) REAL time: 5 secs

Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:4629010b) REAL time: 5 secs

Phase 6.30  Global Clock Region Assignment
Phase 6.30  Global Clock Region Assignment (Checksum:4629010b) REAL time: 5 secs

Phase 7.3  Local Placement Optimization
Phase 7.3  Local Placement Optimization (Checksum:4629010b) REAL time: 5 secs

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:4629010b) REAL time: 5 secs

Phase 9.8  Global Placement
............
..............................
......................................................................................................................................................................................
...............................................................................................................................................................................................................
..........................
Phase 9.8  Global Placement (Checksum:556f780e) REAL time: 9 secs

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:556f780e) REAL time: 9 secs

Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization (Checksum:4d6e0d5e) REAL time: 15 secs

Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization (Checksum:4d6e0d5e) REAL time: 15 secs

Phase 13.34  Placement Validation
Phase 13.34  Placement Validation (Checksum:23324b63) REAL time: 15 secs

Total REAL time to Placer completion: 15 secs
Total CPU  time to Placer completion: 15 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net d/_n2077 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net g/rst_ran2[5]_AND_16_o is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net g/rst_ran1[5]_AND_6_o is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net g/rst_ran2[5]_AND_18_o is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net g/rst_ran1[5]_AND_4_o is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net g/rst_ran1[5]_AND_2_o is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net g/rst_ran1[5]_AND_12_o is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net g/rst_ranop[3]_AND_30_o is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net g/rst_ranop[3]_AND_26_o is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net g/rst_ranop[3]_AND_28_o is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net g/rst_ran1[5]_AND_10_o is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net g/rst_ran2[5]_AND_20_o is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net g/rst_ran2[5]_AND_24_o is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net g/rst_ran1[5]_AND_8_o is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net g/rst_ran2[5]_AND_22_o is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net k/_n0147 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net g/rst_ran2[5]_AND_14_o is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:   18
Slice Logic Utilization:
  Number of Slice Registers:                   366 out of  18,224    2%
    Number used as Flip Flops:                 329
    Number used as Latches:                     37
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                      1,429 out of   9,112   15%
    Number used as logic:                    1,426 out of   9,112   15%
      Number using O6 output only:           1,126
      Number using O5 output only:              26
      Number using O5 and O6:                  274
      Number used as ROM:                        0
    Number used as Memory:                       0 out of   2,176    0%
    Number used exclusively as route-thrus:      3
      Number with same-slice register load:      0
      Number with same-slice carry load:         3
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                   581 out of   2,278   25%
  Number of MUXCYs used:                       172 out of   4,556    3%
  Number of LUT Flip Flop pairs used:        1,482
    Number with an unused Flip Flop:         1,148 out of   1,482   77%
    Number with an unused LUT:                  53 out of   1,482    3%
    Number of fully used LUT-FF pairs:         281 out of   1,482   18%
    Number of unique control sets:              89
    Number of slice register sites lost
      to control set restrictions:             506 out of  18,224    2%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                        52 out of     232   22%
    Number of LOCed IOBs:                       52 out of      52  100%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of      32    0%
  Number of RAMB8BWERs:                          0 out of      64    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       6 out of      16   37%
    Number used as BUFGs:                        6
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     248    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     248    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     248    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            1 out of      32    3%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                4.67

Peak Memory Usage:  377 MB
Total REAL time to MAP completion:  16 secs
Total CPU time to MAP completion:   16 secs

Mapping completed.
See MAP report file "calculator_map.mrp" for details.