I ran into issues while sending this to JLCPCB, but I don't understand enough to explain what. Here is a summary by an AI
Overview
The footprint assigned to U3 (the W25Q128JV SPI Flash) in the KiCad project is too narrow for the physical chip. Attempting to manufacture the board as-is results in a failure during the SMT assembly review process.
Expected Behavior
The 128Mbit W25Q128JVSIQ chip comes in a wide 208-mil SOIC-8 package (~7.9mm tip-to-tip span). The PCB footprint should match these dimensions to allow for proper solder joints.
Actual Behavior
The project currently uses a custom footprint (Winbond:SOIC-8_3.9x4.9mm_P1.27mm) which is a narrow 150-mil package. Because the physical chip is significantly wider than the footprint, the metal leads overhang the pads, causing a high risk of misaligned and cold solder joints.
Steps to Reproduce
1. Export the project Gerbers and CPL files.
2. Submit the PCBA order to JLCPCB (or similar automated assembly service).
3. The engineering review flags U3 with: "Components selected oversized for the pad. Solder pad area is insufficient."
Proposed Solution
Update the footprint for U3 in the schematic and PCB layout to the standard, wider footprint found in the default KiCad libraries:
Package_SO:SOIC-8_5.3x5.3mm_P1.27mm (or Package_SO:SOIC-8_5.23x5.23mm_P1.27mm depending on the KiCad version).
This 208-mil footprint is a mathematically perfect match for the W25Q128JVSIQ and passes automated assembly checks without issue.
I ran into issues while sending this to JLCPCB, but I don't understand enough to explain what. Here is a summary by an AI
Overview
The footprint assigned to U3 (the W25Q128JV SPI Flash) in the KiCad project is too narrow for the physical chip. Attempting to manufacture the board as-is results in a failure during the SMT assembly review process.
Expected Behavior
The 128Mbit W25Q128JVSIQ chip comes in a wide 208-mil SOIC-8 package (~7.9mm tip-to-tip span). The PCB footprint should match these dimensions to allow for proper solder joints.
Actual Behavior
The project currently uses a custom footprint (Winbond:SOIC-8_3.9x4.9mm_P1.27mm) which is a narrow 150-mil package. Because the physical chip is significantly wider than the footprint, the metal leads overhang the pads, causing a high risk of misaligned and cold solder joints.
Steps to Reproduce
Proposed Solution
Update the footprint for U3 in the schematic and PCB layout to the standard, wider footprint found in the default KiCad libraries:
Package_SO:SOIC-8_5.3x5.3mm_P1.27mm (or Package_SO:SOIC-8_5.23x5.23mm_P1.27mm depending on the KiCad version).
This 208-mil footprint is a mathematically perfect match for the W25Q128JVSIQ and passes automated assembly checks without issue.