diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi index 0187d85bdd8d4..74a069eced695 100644 --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi @@ -3,6 +3,7 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include #include #include #include @@ -11,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d0fe133d8e887..0173a712c1231 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -197,17 +197,6 @@ config CLK_KAANAPALI_VIDEOCC Say Y if you want to support video devices and functionality such as video encode/decode. -config CLK_NORD_CAMCC - tristate "Nord Camera Clock Controller" - depends on ARM64 || COMPILE_TEST - select CLK_NORD_GCC - default m if ARCH_QCOM - help - Support for the camera clock controller on Qualcomm Technologies, Inc - Nord devices. - Say Y if you want to support camera devices and functionality such as - capturing pictures. - config CLK_NORD_DISPCC tristate "Nord Display Clock Controller" depends on ARM64 || COMPILE_TEST @@ -219,6 +208,17 @@ config CLK_NORD_DISPCC Say Y if you want to support display devices and functionality such as splash screen. +config CLK_NORD_CAMCC + tristate "Nord Camera Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_NORD_GCC + default m if ARCH_QCOM + help + Support for the camera clock controller on Qualcomm Technologies, Inc + Nord devices. + Say Y if you want to support camera devices and functionality such as + capturing pictures. + config CLK_NORD_GCC tristate "Nord Global Clock Controller" depends on ARM64 || COMPILE_TEST @@ -240,17 +240,6 @@ config CLK_NORD_GPUCC Say Y if you want to support graphics controller devices and functionality such as 3D graphics. -config CLK_NORD_VIDEOCC - tristate "Nord VIDEO Clock Controller" - depends on ARM64 || COMPILE_TEST - select CLK_NORD_GCC - default m if ARCH_QCOM - help - Support for the video clock controller on Qualcomm Technologies, Inc. - Nord devices. - Say Y if you want to support video devices and functionality such as - video encode/decode. - config CLK_SHIKRA_AUDIOCORECC tristate "Shikra Audio Core Clock Controller" depends on ARM64 || COMPILE_TEST @@ -262,6 +251,17 @@ config CLK_SHIKRA_AUDIOCORECC Say Y if you want to use AudioCoreCC clocks required to support audio devices and it's functionality. +config CLK_NORD_VIDEOCC + tristate "Nord VIDEO Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_NORD_GCC + default m if ARCH_QCOM + help + Support for the video clock controller on Qualcomm Technologies, Inc. + Nord devices. + Say Y if you want to support video devices and functionality such as + video encode/decode. + config CLK_SHIKRA_GCC tristate "Shikra Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 4e1fd5a903070..3489b6dc1d55f 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -48,7 +48,8 @@ obj-$(CONFIG_CLK_NORD_DISPCC) += dispcc0-nord.o dispcc1-nord.o obj-$(CONFIG_CLK_NORD_GCC) += gcc-nord.o negcc-nord.o nwgcc-nord.o segcc-nord.o obj-$(CONFIG_CLK_NORD_GPUCC) += gpucc-nord.o gpu2cc-nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o -obj-$(CONFIG_CLK_NORD_VIDEOCC) += videocc-nord.o +obj-$(CONFIG_CLK_NORD_VIDEOCC) += videocc-glymur.o +obj-$(CONFIG_CLK_SHIKRA_AUDIOCORECC) += audiocorecc-shikra.o obj-$(CONFIG_CLK_SHIKRA_GCC) += gcc-shikra.o obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o diff --git a/drivers/clk/qcom/nwgcc-nord.c b/drivers/clk/qcom/nwgcc-nord.c index e061c0623e9a4..280558f15748c 100644 --- a/drivers/clk/qcom/nwgcc-nord.c +++ b/drivers/clk/qcom/nwgcc-nord.c @@ -623,6 +623,9 @@ static const struct qcom_reset_map nw_gcc_nord_resets[] = { [NW_GCC_GPU_2_BCR] = { 0x24000 }, [NW_GCC_GPU_BCR] = { 0x23000 }, [NW_GCC_VIDEO_BCR] = { 0x1a000 }, + [NW_GCC_VIDEO_AXI0_CLK_ARES] = { 0x1a008, 2 }, + [NW_GCC_VIDEO_AXI0C_CLK_ARES] = { 0x1a01c, 2 }, + [NW_GCC_VIDEO_AXI1_CLK_ARES] = { 0x1a030, 2 }, }; static const u32 nw_gcc_nord_critical_cbcrs[] = { diff --git a/drivers/clk/qcom/videocc-glymur.c b/drivers/clk/qcom/videocc-glymur.c index 18313a65e78d9..2776140de3555 100644 --- a/drivers/clk/qcom/videocc-glymur.c +++ b/drivers/clk/qcom/videocc-glymur.c @@ -37,6 +37,10 @@ static const struct pll_vco taycan_eko_t_vco[] = { { 249600000, 2500000000, 0 }, }; +static const struct pll_vco lucid_ole_vco[] = { + { 249600000, 2300000000, 0 }, +}; + /* 720.0 MHz Configuration */ static const struct alpha_pll_config video_cc_pll0_config = { .l = 0x25, @@ -48,6 +52,21 @@ static const struct alpha_pll_config video_cc_pll0_config = { .user_ctl_hi_val = 0x00000002, }; +/* 720.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll0_config_nord = { + .l = 0x25, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00400005, +}; + static struct clk_alpha_pll video_cc_pll0 = { .offset = 0x0, .config = &video_cc_pll0_config, @@ -112,6 +131,15 @@ static struct clk_rcg2 video_cc_ahb_clk_src = { }, }; +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_nord[] = { + F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1305000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1440000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1680000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), @@ -508,12 +536,22 @@ static const struct qcom_cc_desc video_cc_glymur_desc = { static const struct of_device_id video_cc_glymur_match_table[] = { { .compatible = "qcom,glymur-videocc" }, + { .compatible = "qcom,nord-videocc" }, { } }; MODULE_DEVICE_TABLE(of, video_cc_glymur_match_table); static int video_cc_glymur_probe(struct platform_device *pdev) { + if (of_device_is_compatible(pdev->dev.of_node, "qcom,nord-videocc")) { + video_cc_pll0.vco_table = lucid_ole_vco; + video_cc_pll0.num_vco = ARRAY_SIZE(lucid_ole_vco); + video_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + video_cc_pll0.config = &video_cc_pll0_config_nord; + + video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_nord; + } + return qcom_cc_probe(pdev, &video_cc_glymur_desc); } diff --git a/drivers/clk/qcom/videocc-nord.c b/drivers/clk/qcom/videocc-nord.c deleted file mode 100644 index ee73e89a01daa..0000000000000 --- a/drivers/clk/qcom/videocc-nord.c +++ /dev/null @@ -1,507 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -#include -#include -#include -#include - -#include - -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "clk-regmap-divider.h" -#include "clk-regmap-mux.h" -#include "common.h" -#include "gdsc.h" -#include "reset.h" - -enum { - DT_BI_TCXO, - DT_IFACE, -}; - -enum { - P_BI_TCXO, - P_SLEEP_CLK, - P_VIDEO_CC_PLL0_OUT_MAIN, -}; - -static const struct pll_vco lucid_ole_vco[] = { - { 249600000, 2300000000, 0 }, -}; - -/* 720.0 MHz Configuration */ -static const struct alpha_pll_config video_cc_pll0_config = { - .l = 0x25, - .alpha = 0x8000, - .config_ctl_val = 0x20485699, - .config_ctl_hi_val = 0x00182261, - .config_ctl_hi1_val = 0x82aa299c, - .test_ctl_val = 0x00000000, - .test_ctl_hi_val = 0x00000003, - .test_ctl_hi1_val = 0x00009000, - .test_ctl_hi2_val = 0x00000034, - .user_ctl_val = 0x00000000, - .user_ctl_hi_val = 0x00400005, -}; - -static struct clk_alpha_pll video_cc_pll0 = { - .offset = 0x0, - .config = &video_cc_pll0_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr = { - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_pll0", - .parent_data = &(const struct clk_parent_data) { - .index = DT_BI_TCXO, - }, - .num_parents = 1, - .ops = &clk_alpha_pll_lucid_evo_ops, - }, - }, -}; - -static const struct parent_map video_cc_parent_map_0[] = { - { P_BI_TCXO, 0 }, -}; - -static const struct clk_parent_data video_cc_parent_data_0[] = { - { .index = DT_BI_TCXO }, -}; - -static const struct parent_map video_cc_parent_map_1[] = { - { P_BI_TCXO, 0 }, - { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, -}; - -static const struct clk_parent_data video_cc_parent_data_1[] = { - { .index = DT_BI_TCXO }, - { .hw = &video_cc_pll0.clkr.hw }, -}; - -static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 video_cc_ahb_clk_src = { - .cmd_rcgr = 0x8018, - .mnd_width = 0, - .hid_width = 5, - .parent_map = video_cc_parent_map_0, - .freq_tbl = ftbl_video_cc_ahb_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "video_cc_ahb_clk_src", - .parent_data = video_cc_parent_data_0, - .num_parents = ARRAY_SIZE(video_cc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { - F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), - F(1305000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), - F(1440000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), - F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), - F(1680000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 video_cc_mvs0_clk_src = { - .cmd_rcgr = 0x8000, - .mnd_width = 0, - .hid_width = 5, - .parent_map = video_cc_parent_map_1, - .freq_tbl = ftbl_video_cc_mvs0_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0_clk_src", - .parent_data = video_cc_parent_data_1, - .num_parents = ARRAY_SIZE(video_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 video_cc_xo_clk_src = { - .cmd_rcgr = 0x80f8, - .mnd_width = 0, - .hid_width = 5, - .parent_map = video_cc_parent_map_0, - .freq_tbl = ftbl_video_cc_ahb_clk_src, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "video_cc_xo_clk_src", - .parent_data = video_cc_parent_data_0, - .num_parents = ARRAY_SIZE(video_cc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_regmap_div video_cc_mvs0_div_clk_src = { - .reg = 0x809c, - .shift = 0, - .width = 4, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0_div_clk_src", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs0_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_regmap_div_ro_ops, - }, -}; - -static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = { - .reg = 0x8060, - .shift = 0, - .width = 4, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0c_div2_div_clk_src", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs0_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_regmap_div_ro_ops, - }, -}; - -static struct clk_regmap_div video_cc_mvs1_div_clk_src = { - .reg = 0x80d8, - .shift = 0, - .width = 4, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs1_div_clk_src", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs0_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_regmap_div_ro_ops, - }, -}; - -static struct clk_branch video_cc_mvs0_clk = { - .halt_reg = 0x807c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x807c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x807c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs0_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_mvs0_freerun_clk = { - .halt_reg = 0x808c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x808c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0_freerun_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs0_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_mvs0_shift_clk = { - .halt_reg = 0x8114, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x8114, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x8114, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0_shift_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_xo_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_mvs0c_clk = { - .halt_reg = 0x804c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x804c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0c_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs0c_div2_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_mvs0c_freerun_clk = { - .halt_reg = 0x805c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x805c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0c_freerun_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs0c_div2_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_mvs0c_shift_clk = { - .halt_reg = 0x811c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x811c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x811c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0c_shift_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_xo_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_mvs1_clk = { - .halt_reg = 0x80b8, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x80b8, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x80b8, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs1_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs1_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_mvs1_freerun_clk = { - .halt_reg = 0x80c8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x80c8, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs1_freerun_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs1_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_mvs1_shift_clk = { - .halt_reg = 0x8118, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x8118, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x8118, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs1_shift_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_xo_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct gdsc video_cc_mvs0c_gdsc = { - .gdscr = 0x8034, - .en_rest_wait_val = 0x2, - .en_few_wait_val = 0x2, - .clk_dis_wait_val = 0x6, - .pd = { - .name = "video_cc_mvs0c_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, -}; - -static struct gdsc video_cc_mvs0_gdsc = { - .gdscr = 0x8068, - .en_rest_wait_val = 0x2, - .en_few_wait_val = 0x2, - .clk_dis_wait_val = 0x6, - .pd = { - .name = "video_cc_mvs0_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .parent = &video_cc_mvs0c_gdsc.pd, - .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, -}; - -static struct gdsc video_cc_mvs1_gdsc = { - .gdscr = 0x80a4, - .en_rest_wait_val = 0x2, - .en_few_wait_val = 0x2, - .clk_dis_wait_val = 0x6, - .pd = { - .name = "video_cc_mvs1_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, -}; - -static struct clk_regmap *video_cc_nord_clocks[] = { - [VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr, - [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr, - [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr, - [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr, - [VIDEO_CC_MVS0_FREERUN_CLK] = &video_cc_mvs0_freerun_clk.clkr, - [VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr, - [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr, - [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr, - [VIDEO_CC_MVS0C_FREERUN_CLK] = &video_cc_mvs0c_freerun_clk.clkr, - [VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr, - [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr, - [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr, - [VIDEO_CC_MVS1_FREERUN_CLK] = &video_cc_mvs1_freerun_clk.clkr, - [VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr, - [VIDEO_CC_PLL0] = &video_cc_pll0.clkr, - [VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr, -}; - -static struct gdsc *video_cc_nord_gdscs[] = { - [VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc, - [VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc, - [VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc, -}; - -static const struct qcom_reset_map video_cc_nord_resets[] = { - [VIDEO_CC_INTERFACE_BCR] = { 0x80dc }, - [VIDEO_CC_MVS0_BCR] = { 0x8064 }, - [VIDEO_CC_MVS0C_CLK_ARES] = { 0x804c, 2 }, - [VIDEO_CC_MVS0C_BCR] = { 0x8030 }, - [VIDEO_CC_MVS1_BCR] = { 0x80a0 }, -}; - -static struct clk_alpha_pll *video_cc_nord_plls[] = { - &video_cc_pll0, -}; - -static const u32 video_cc_nord_critical_cbcrs[] = { - 0x80e0, /* VIDEO_CC_AHB_CLK */ - 0x8138, /* VIDEO_CC_SLEEP_CLK */ - 0x8110, /* VIDEO_CC_XO_CLK */ -}; - -static const struct regmap_config video_cc_nord_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0xa060, - .fast_io = true, -}; - -static void videocc_nord_regs_configure(struct device *dev, struct regmap *regmap) -{ - /* - * Enable clk_on sync for MVS0 and MVS0_FREERUN clocks via - * VIDEO_CC_SPARE1 during core reset by default. - */ - regmap_set_bits(regmap, 0x9f24, BIT(0)); -} - -static const struct qcom_cc_driver_data video_cc_nord_driver_data = { - .alpha_plls = video_cc_nord_plls, - .num_alpha_plls = ARRAY_SIZE(video_cc_nord_plls), - .clk_cbcrs = video_cc_nord_critical_cbcrs, - .num_clk_cbcrs = ARRAY_SIZE(video_cc_nord_critical_cbcrs), - .clk_regs_configure = videocc_nord_regs_configure, -}; - -static const struct qcom_cc_desc video_cc_nord_desc = { - .config = &video_cc_nord_regmap_config, - .clks = video_cc_nord_clocks, - .num_clks = ARRAY_SIZE(video_cc_nord_clocks), - .resets = video_cc_nord_resets, - .num_resets = ARRAY_SIZE(video_cc_nord_resets), - .gdscs = video_cc_nord_gdscs, - .num_gdscs = ARRAY_SIZE(video_cc_nord_gdscs), - .use_rpm = true, - .driver_data = &video_cc_nord_driver_data, -}; - -static const struct of_device_id video_cc_nord_match_table[] = { - { .compatible = "qcom,nord-videocc" }, - { } -}; -MODULE_DEVICE_TABLE(of, video_cc_nord_match_table); - -static int video_cc_nord_probe(struct platform_device *pdev) -{ - return qcom_cc_probe(pdev, &video_cc_nord_desc); -} - -static struct platform_driver video_cc_nord_driver = { - .probe = video_cc_nord_probe, - .driver = { - .name = "videocc-nord", - .of_match_table = video_cc_nord_match_table, - }, -}; - -module_platform_driver(video_cc_nord_driver); - -MODULE_DESCRIPTION("QTI VIDEOCC Nord Driver"); -MODULE_LICENSE("GPL"); diff --git a/include/dt-bindings/clock/qcom,nord-nwgcc.h b/include/dt-bindings/clock/qcom,nord-nwgcc.h index b6253dd2aa85a..8beaa129aa814 100644 --- a/include/dt-bindings/clock/qcom,nord-nwgcc.h +++ b/include/dt-bindings/clock/qcom,nord-nwgcc.h @@ -65,5 +65,8 @@ #define NW_GCC_GPU_2_BCR 6 #define NW_GCC_GPU_BCR 7 #define NW_GCC_VIDEO_BCR 8 +#define NW_GCC_VIDEO_AXI0_CLK_ARES 9 +#define NW_GCC_VIDEO_AXI0C_CLK_ARES 10 +#define NW_GCC_VIDEO_AXI1_CLK_ARES 11 #endif diff --git a/include/dt-bindings/clock/qcom,nord-videocc.h b/include/dt-bindings/clock/qcom,nord-videocc.h deleted file mode 100644 index 8d75460211099..0000000000000 --- a/include/dt-bindings/clock/qcom,nord-videocc.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_NORD_H -#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_NORD_H - -/* VIDEO_CC clocks */ -#define VIDEO_CC_AHB_CLK_SRC 0 -#define VIDEO_CC_MVS0_CLK 1 -#define VIDEO_CC_MVS0_CLK_SRC 2 -#define VIDEO_CC_MVS0_DIV_CLK_SRC 3 -#define VIDEO_CC_MVS0_FREERUN_CLK 4 -#define VIDEO_CC_MVS0_SHIFT_CLK 5 -#define VIDEO_CC_MVS0C_CLK 6 -#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 7 -#define VIDEO_CC_MVS0C_FREERUN_CLK 8 -#define VIDEO_CC_MVS0C_SHIFT_CLK 9 -#define VIDEO_CC_MVS1_CLK 10 -#define VIDEO_CC_MVS1_DIV_CLK_SRC 11 -#define VIDEO_CC_MVS1_FREERUN_CLK 12 -#define VIDEO_CC_MVS1_SHIFT_CLK 13 -#define VIDEO_CC_PLL0 14 -#define VIDEO_CC_SLEEP_CLK_SRC 15 -#define VIDEO_CC_XO_CLK_SRC 16 - -/* VIDEO_CC power domains */ -#define VIDEO_CC_MVS0_GDSC 0 -#define VIDEO_CC_MVS0C_GDSC 1 -#define VIDEO_CC_MVS1_GDSC 2 - -/* VIDEO_CC resets */ -#define VIDEO_CC_INTERFACE_BCR 0 -#define VIDEO_CC_MVS0_BCR 1 -#define VIDEO_CC_MVS0C_CLK_ARES 2 -#define VIDEO_CC_MVS0C_BCR 3 -#define VIDEO_CC_MVS1_BCR 4 - -#endif