From 523f3cb488510f26dc03770a8a4fa36b91922261 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 6 Aug 2026 16:06:56 +0530 Subject: [PATCH 01/11] Revert "FROMLIST: dt-bindings: clock: qcom: Add video clock controller on Nord SoC" This reverts commit a5604d43be11f6d2ebd5c77f2a7c2426fa9dd6cd. Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sm8450-videocc.yaml | 2 - include/dt-bindings/clock/qcom,nord-videocc.h | 40 ------------------- 2 files changed, 42 deletions(-) delete mode 100644 include/dt-bindings/clock/qcom,nord-videocc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index 9b9878e9b9cfc..5d77029bfaf88 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -17,7 +17,6 @@ description: | See also: include/dt-bindings/clock/qcom,glymur-videocc.h include/dt-bindings/clock/qcom,kaanapali-videocc.h - include/dt-bindings/clock/qcom,nord-videocc.h include/dt-bindings/clock/qcom,sm8450-videocc.h include/dt-bindings/clock/qcom,sm8650-videocc.h include/dt-bindings/clock/qcom,sm8750-videocc.h @@ -28,7 +27,6 @@ properties: enum: - qcom,glymur-videocc - qcom,kaanapali-videocc - - qcom,nord-videocc - qcom,sm8450-videocc - qcom,sm8475-videocc - qcom,sm8550-videocc diff --git a/include/dt-bindings/clock/qcom,nord-videocc.h b/include/dt-bindings/clock/qcom,nord-videocc.h deleted file mode 100644 index 8d75460211099..0000000000000 --- a/include/dt-bindings/clock/qcom,nord-videocc.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_NORD_H -#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_NORD_H - -/* VIDEO_CC clocks */ -#define VIDEO_CC_AHB_CLK_SRC 0 -#define VIDEO_CC_MVS0_CLK 1 -#define VIDEO_CC_MVS0_CLK_SRC 2 -#define VIDEO_CC_MVS0_DIV_CLK_SRC 3 -#define VIDEO_CC_MVS0_FREERUN_CLK 4 -#define VIDEO_CC_MVS0_SHIFT_CLK 5 -#define VIDEO_CC_MVS0C_CLK 6 -#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 7 -#define VIDEO_CC_MVS0C_FREERUN_CLK 8 -#define VIDEO_CC_MVS0C_SHIFT_CLK 9 -#define VIDEO_CC_MVS1_CLK 10 -#define VIDEO_CC_MVS1_DIV_CLK_SRC 11 -#define VIDEO_CC_MVS1_FREERUN_CLK 12 -#define VIDEO_CC_MVS1_SHIFT_CLK 13 -#define VIDEO_CC_PLL0 14 -#define VIDEO_CC_SLEEP_CLK_SRC 15 -#define VIDEO_CC_XO_CLK_SRC 16 - -/* VIDEO_CC power domains */ -#define VIDEO_CC_MVS0_GDSC 0 -#define VIDEO_CC_MVS0C_GDSC 1 -#define VIDEO_CC_MVS1_GDSC 2 - -/* VIDEO_CC resets */ -#define VIDEO_CC_INTERFACE_BCR 0 -#define VIDEO_CC_MVS0_BCR 1 -#define VIDEO_CC_MVS0C_CLK_ARES 2 -#define VIDEO_CC_MVS0C_BCR 3 -#define VIDEO_CC_MVS1_BCR 4 - -#endif From 7ebb16c6e1cced6fd4ae384a6c133e8243b834b2 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 6 Aug 2026 16:11:44 +0530 Subject: [PATCH 02/11] Revert "FROMLIST: dt-bindings: clock: qcom: Add support for Camera Clock Controller for Nord" This reverts commit 114185396611d008d541b18a85fc1ba13a07ccbf. Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sm8450-camcc.yaml | 2 - include/dt-bindings/clock/qcom,nord-camcc.h | 167 ------------------ 2 files changed, 169 deletions(-) delete mode 100644 include/dt-bindings/clock/qcom,nord-camcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index 8e460df9f7444..8492a7ef73245 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -18,7 +18,6 @@ description: | See also: include/dt-bindings/clock/qcom,kaanapali-camcc.h include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h - include/dt-bindings/clock/qcom,nord-camcc.h include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h include/dt-bindings/clock/qcom,sm8650-camcc.h @@ -30,7 +29,6 @@ properties: enum: - qcom,kaanapali-cambistmclkcc - qcom,kaanapali-camcc - - qcom,nord-camcc - qcom,sm8450-camcc - qcom,sm8475-camcc - qcom,sm8550-camcc diff --git a/include/dt-bindings/clock/qcom,nord-camcc.h b/include/dt-bindings/clock/qcom,nord-camcc.h deleted file mode 100644 index 655fef2084a58..0000000000000 --- a/include/dt-bindings/clock/qcom,nord-camcc.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_NORD_H -#define _DT_BINDINGS_CLK_QCOM_CAM_CC_NORD_H - -/* CAM_CC clocks */ -#define CAM_CC_CAMNOC_DCD_XO_CLK 0 -#define CAM_CC_CAMNOC_NRT_AXI_CLK 1 -#define CAM_CC_CAMNOC_RT_AXI_CLK 2 -#define CAM_CC_CAMNOC_RT_AXI_CLK_SRC 3 -#define CAM_CC_CAMNOC_XO_CLK 4 -#define CAM_CC_CCI_0_CLK 5 -#define CAM_CC_CCI_0_CLK_SRC 6 -#define CAM_CC_CCI_1_CLK 7 -#define CAM_CC_CCI_1_CLK_SRC 8 -#define CAM_CC_CCI_2_CLK 9 -#define CAM_CC_CCI_2_CLK_SRC 10 -#define CAM_CC_CCI_3_CLK 11 -#define CAM_CC_CCI_3_CLK_SRC 12 -#define CAM_CC_CCI_4_CLK 13 -#define CAM_CC_CCI_4_CLK_SRC 14 -#define CAM_CC_CCU_FAST_AHB_CLK 15 -#define CAM_CC_CORE_AHB_CLK 16 -#define CAM_CC_CPHY_RX_CLK_SRC 17 -#define CAM_CC_CSI0PHYTIMER_CLK 18 -#define CAM_CC_CSI0PHYTIMER_CLK_SRC 19 -#define CAM_CC_CSI1PHYTIMER_CLK 20 -#define CAM_CC_CSI1PHYTIMER_CLK_SRC 21 -#define CAM_CC_CSI2PHYTIMER_CLK 22 -#define CAM_CC_CSI2PHYTIMER_CLK_SRC 23 -#define CAM_CC_CSI3PHYTIMER_CLK 24 -#define CAM_CC_CSI3PHYTIMER_CLK_SRC 25 -#define CAM_CC_CSI4PHYTIMER_CLK 26 -#define CAM_CC_CSI4PHYTIMER_CLK_SRC 27 -#define CAM_CC_CSID_CLK 28 -#define CAM_CC_CSID_CLK_SRC 29 -#define CAM_CC_CSID_CSIPHY_RX_CLK 30 -#define CAM_CC_CSIPHY0_CLK 31 -#define CAM_CC_CSIPHY1_CLK 32 -#define CAM_CC_CSIPHY2_CLK 33 -#define CAM_CC_CSIPHY3_CLK 34 -#define CAM_CC_CSIPHY4_CLK 35 -#define CAM_CC_FAST_AHB_CLK_SRC 36 -#define CAM_CC_GDSC_CLK 37 -#define CAM_CC_ICP_0_AHB_CLK 38 -#define CAM_CC_ICP_0_CLK 39 -#define CAM_CC_ICP_0_CLK_SRC 40 -#define CAM_CC_ICP_1_AHB_CLK 41 -#define CAM_CC_ICP_1_CLK 42 -#define CAM_CC_ICP_1_CLK_SRC 43 -#define CAM_CC_IFE_0_MAIN_CLK 44 -#define CAM_CC_IFE_0_MAIN_CLK_SRC 45 -#define CAM_CC_IFE_0_MAIN_FAST_AHB_CLK 46 -#define CAM_CC_IFE_0_PCP_CLK 47 -#define CAM_CC_IFE_0_PCP_FAST_AHB_CLK 48 -#define CAM_CC_IFE_0_SCALAR_CLK 49 -#define CAM_CC_IFE_0_SCALAR_FAST_AHB_CLK 50 -#define CAM_CC_IFE_0_TMC_CLK 51 -#define CAM_CC_IFE_0_TMC_FAST_AHB_CLK 52 -#define CAM_CC_IFE_1_MAIN_CLK 53 -#define CAM_CC_IFE_1_MAIN_CLK_SRC 54 -#define CAM_CC_IFE_1_MAIN_FAST_AHB_CLK 55 -#define CAM_CC_IFE_1_PCP_CLK 56 -#define CAM_CC_IFE_1_PCP_FAST_AHB_CLK 57 -#define CAM_CC_IFE_1_SCALAR_CLK 58 -#define CAM_CC_IFE_1_SCALAR_FAST_AHB_CLK 59 -#define CAM_CC_IFE_1_TMC_CLK 60 -#define CAM_CC_IFE_1_TMC_FAST_AHB_CLK 61 -#define CAM_CC_IFE_2_MAIN_CLK 62 -#define CAM_CC_IFE_2_MAIN_CLK_SRC 63 -#define CAM_CC_IFE_2_MAIN_FAST_AHB_CLK 64 -#define CAM_CC_IFE_2_PCP_CLK 65 -#define CAM_CC_IFE_2_PCP_FAST_AHB_CLK 66 -#define CAM_CC_IFE_2_SCALAR_CLK 67 -#define CAM_CC_IFE_2_SCALAR_FAST_AHB_CLK 68 -#define CAM_CC_IFE_2_TMC_CLK 69 -#define CAM_CC_IFE_2_TMC_FAST_AHB_CLK 70 -#define CAM_CC_IFE_LITE_AHB_CLK 71 -#define CAM_CC_IFE_LITE_CLK 72 -#define CAM_CC_IFE_LITE_CLK_SRC 73 -#define CAM_CC_IFE_LITE_CPHY_RX_CLK 74 -#define CAM_CC_IFE_LITE_CSID_CLK 75 -#define CAM_CC_IFE_LITE_CSID_CLK_SRC 76 -#define CAM_CC_IPE_0_AHB_CLK 77 -#define CAM_CC_IPE_0_CLK 78 -#define CAM_CC_IPE_0_CLK_SRC 79 -#define CAM_CC_IPE_0_FAST_AHB_CLK 80 -#define CAM_CC_IPE_1_AHB_CLK 81 -#define CAM_CC_IPE_1_CLK 82 -#define CAM_CC_IPE_1_CLK_SRC 83 -#define CAM_CC_IPE_1_FAST_AHB_CLK 84 -#define CAM_CC_PLL0 85 -#define CAM_CC_PLL0_OUT_EVEN 86 -#define CAM_CC_PLL0_OUT_ODD 87 -#define CAM_CC_PLL2 88 -#define CAM_CC_PLL2_OUT_EVEN 89 -#define CAM_CC_PLL3 90 -#define CAM_CC_PLL3_OUT_EVEN 91 -#define CAM_CC_PLL4 92 -#define CAM_CC_PLL4_OUT_EVEN 93 -#define CAM_CC_PLL5 94 -#define CAM_CC_PLL5_OUT_EVEN 95 -#define CAM_CC_PLL6 96 -#define CAM_CC_PLL6_OUT_EVEN 97 -#define CAM_CC_QDSS_DEBUG_CLK 98 -#define CAM_CC_QDSS_DEBUG_CLK_SRC 99 -#define CAM_CC_QDSS_DEBUG_XO_CLK 100 -#define CAM_CC_QUP_AHBM_CLK 101 -#define CAM_CC_QUP_AHBM_CLK_SRC 102 -#define CAM_CC_QUP_CORE_2X_CLK 103 -#define CAM_CC_QUP_CORE_2X_CLK_SRC 104 -#define CAM_CC_QUP_CORE_2X_DIV_CLK_SRC 105 -#define CAM_CC_QUP_CORE_CLK 106 -#define CAM_CC_QUP_SE_CLK 107 -#define CAM_CC_QUP_SE_CLK_SRC 108 -#define CAM_CC_QUP_SLEEP_CLK 109 -#define CAM_CC_SFE_LITE_0_CLK 110 -#define CAM_CC_SFE_LITE_0_FAST_AHB_CLK 111 -#define CAM_CC_SFE_LITE_1_CLK 112 -#define CAM_CC_SFE_LITE_1_FAST_AHB_CLK 113 -#define CAM_CC_SFE_LITE_2_CLK 114 -#define CAM_CC_SFE_LITE_2_FAST_AHB_CLK 115 -#define CAM_CC_SLEEP_CLK 116 -#define CAM_CC_SLEEP_CLK_SRC 117 -#define CAM_CC_SLOW_AHB_CLK_SRC 118 -#define CAM_CC_SM_OBS_CLK 119 -#define CAM_CC_TOP_AHB_CLK 120 -#define CAM_CC_TOP_FAST_AHB_CLK 121 -#define CAM_CC_TOP_IFE_0_CLK 122 -#define CAM_CC_TOP_IFE_1_CLK 123 -#define CAM_CC_TOP_IFE_2_CLK 124 -#define CAM_CC_TOP_IFE_LITE_CLK 125 -#define CAM_CC_TOP_IPE_0_CLK 126 -#define CAM_CC_TOP_IPE_1_CLK 127 -#define CAM_CC_TOP_QUP_AHBM_CLK 128 -#define CAM_CC_TOP_SFE_LITE_0_CLK 129 -#define CAM_CC_TOP_SFE_LITE_1_CLK 130 -#define CAM_CC_TOP_SFE_LITE_2_CLK 131 -#define CAM_CC_TPG_CSIPHY_RX_CLK 132 -#define CAM_CC_XO_CLK_SRC 133 - -/* CAM_CC power domains */ -#define CAM_CC_IFE_0_GDSC 0 -#define CAM_CC_IFE_1_GDSC 1 -#define CAM_CC_IFE_2_GDSC 2 -#define CAM_CC_IPE_0_GDSC 3 -#define CAM_CC_IPE_1_GDSC 4 -#define CAM_CC_TITAN_TOP_GDSC 5 - -/* CAM_CC resets */ -#define CAM_CC_CCU_BCR 0 -#define CAM_CC_ICP_0_BCR 1 -#define CAM_CC_ICP_1_BCR 2 -#define CAM_CC_IFE_0_BCR 3 -#define CAM_CC_IFE_1_BCR 4 -#define CAM_CC_IFE_2_BCR 5 -#define CAM_CC_IPE_0_BCR 6 -#define CAM_CC_IPE_1_BCR 7 -#define CAM_CC_QDSS_DEBUG_BCR 8 -#define CAM_CC_SFE_LITE_0_BCR 9 -#define CAM_CC_SFE_LITE_1_BCR 10 -#define CAM_CC_SFE_LITE_2_BCR 11 - -#endif From c10c392bcd8b4c71f953f2ff6d10ec70d101a406 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 6 Aug 2026 12:24:00 +0530 Subject: [PATCH 03/11] Revert "FROMLIST: clk: qcom: videocc-nord: Add video clock controller driver for Nord" This reverts commit f7978ea1fe3e334db0bed1d9f3487a2339b5a440. Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 11 - drivers/clk/qcom/Makefile | 2 +- drivers/clk/qcom/videocc-nord.c | 507 -------------------------------- 3 files changed, 1 insertion(+), 519 deletions(-) delete mode 100644 drivers/clk/qcom/videocc-nord.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d0fe133d8e887..36020b208734c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -240,17 +240,6 @@ config CLK_NORD_GPUCC Say Y if you want to support graphics controller devices and functionality such as 3D graphics. -config CLK_NORD_VIDEOCC - tristate "Nord VIDEO Clock Controller" - depends on ARM64 || COMPILE_TEST - select CLK_NORD_GCC - default m if ARCH_QCOM - help - Support for the video clock controller on Qualcomm Technologies, Inc. - Nord devices. - Say Y if you want to support video devices and functionality such as - video encode/decode. - config CLK_SHIKRA_AUDIOCORECC tristate "Shikra Audio Core Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 4e1fd5a903070..5e0cbe4c09228 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -48,7 +48,7 @@ obj-$(CONFIG_CLK_NORD_DISPCC) += dispcc0-nord.o dispcc1-nord.o obj-$(CONFIG_CLK_NORD_GCC) += gcc-nord.o negcc-nord.o nwgcc-nord.o segcc-nord.o obj-$(CONFIG_CLK_NORD_GPUCC) += gpucc-nord.o gpu2cc-nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o -obj-$(CONFIG_CLK_NORD_VIDEOCC) += videocc-nord.o +obj-$(CONFIG_CLK_SHIKRA_AUDIOCORECC) += audiocorecc-shikra.o obj-$(CONFIG_CLK_SHIKRA_GCC) += gcc-shikra.o obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o diff --git a/drivers/clk/qcom/videocc-nord.c b/drivers/clk/qcom/videocc-nord.c deleted file mode 100644 index ee73e89a01daa..0000000000000 --- a/drivers/clk/qcom/videocc-nord.c +++ /dev/null @@ -1,507 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -#include -#include -#include -#include - -#include - -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "clk-regmap-divider.h" -#include "clk-regmap-mux.h" -#include "common.h" -#include "gdsc.h" -#include "reset.h" - -enum { - DT_BI_TCXO, - DT_IFACE, -}; - -enum { - P_BI_TCXO, - P_SLEEP_CLK, - P_VIDEO_CC_PLL0_OUT_MAIN, -}; - -static const struct pll_vco lucid_ole_vco[] = { - { 249600000, 2300000000, 0 }, -}; - -/* 720.0 MHz Configuration */ -static const struct alpha_pll_config video_cc_pll0_config = { - .l = 0x25, - .alpha = 0x8000, - .config_ctl_val = 0x20485699, - .config_ctl_hi_val = 0x00182261, - .config_ctl_hi1_val = 0x82aa299c, - .test_ctl_val = 0x00000000, - .test_ctl_hi_val = 0x00000003, - .test_ctl_hi1_val = 0x00009000, - .test_ctl_hi2_val = 0x00000034, - .user_ctl_val = 0x00000000, - .user_ctl_hi_val = 0x00400005, -}; - -static struct clk_alpha_pll video_cc_pll0 = { - .offset = 0x0, - .config = &video_cc_pll0_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr = { - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_pll0", - .parent_data = &(const struct clk_parent_data) { - .index = DT_BI_TCXO, - }, - .num_parents = 1, - .ops = &clk_alpha_pll_lucid_evo_ops, - }, - }, -}; - -static const struct parent_map video_cc_parent_map_0[] = { - { P_BI_TCXO, 0 }, -}; - -static const struct clk_parent_data video_cc_parent_data_0[] = { - { .index = DT_BI_TCXO }, -}; - -static const struct parent_map video_cc_parent_map_1[] = { - { P_BI_TCXO, 0 }, - { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, -}; - -static const struct clk_parent_data video_cc_parent_data_1[] = { - { .index = DT_BI_TCXO }, - { .hw = &video_cc_pll0.clkr.hw }, -}; - -static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 video_cc_ahb_clk_src = { - .cmd_rcgr = 0x8018, - .mnd_width = 0, - .hid_width = 5, - .parent_map = video_cc_parent_map_0, - .freq_tbl = ftbl_video_cc_ahb_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "video_cc_ahb_clk_src", - .parent_data = video_cc_parent_data_0, - .num_parents = ARRAY_SIZE(video_cc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { - F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), - F(1305000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), - F(1440000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), - F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), - F(1680000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 video_cc_mvs0_clk_src = { - .cmd_rcgr = 0x8000, - .mnd_width = 0, - .hid_width = 5, - .parent_map = video_cc_parent_map_1, - .freq_tbl = ftbl_video_cc_mvs0_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0_clk_src", - .parent_data = video_cc_parent_data_1, - .num_parents = ARRAY_SIZE(video_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 video_cc_xo_clk_src = { - .cmd_rcgr = 0x80f8, - .mnd_width = 0, - .hid_width = 5, - .parent_map = video_cc_parent_map_0, - .freq_tbl = ftbl_video_cc_ahb_clk_src, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "video_cc_xo_clk_src", - .parent_data = video_cc_parent_data_0, - .num_parents = ARRAY_SIZE(video_cc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_regmap_div video_cc_mvs0_div_clk_src = { - .reg = 0x809c, - .shift = 0, - .width = 4, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0_div_clk_src", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs0_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_regmap_div_ro_ops, - }, -}; - -static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = { - .reg = 0x8060, - .shift = 0, - .width = 4, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0c_div2_div_clk_src", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs0_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_regmap_div_ro_ops, - }, -}; - -static struct clk_regmap_div video_cc_mvs1_div_clk_src = { - .reg = 0x80d8, - .shift = 0, - .width = 4, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs1_div_clk_src", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs0_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_regmap_div_ro_ops, - }, -}; - -static struct clk_branch video_cc_mvs0_clk = { - .halt_reg = 0x807c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x807c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x807c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs0_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_mvs0_freerun_clk = { - .halt_reg = 0x808c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x808c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0_freerun_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs0_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_mvs0_shift_clk = { - .halt_reg = 0x8114, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x8114, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x8114, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0_shift_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_xo_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_mvs0c_clk = { - .halt_reg = 0x804c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x804c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0c_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs0c_div2_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_mvs0c_freerun_clk = { - .halt_reg = 0x805c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x805c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0c_freerun_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs0c_div2_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_mvs0c_shift_clk = { - .halt_reg = 0x811c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x811c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x811c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs0c_shift_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_xo_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_mvs1_clk = { - .halt_reg = 0x80b8, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x80b8, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x80b8, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs1_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs1_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_mvs1_freerun_clk = { - .halt_reg = 0x80c8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x80c8, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs1_freerun_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_mvs1_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_mvs1_shift_clk = { - .halt_reg = 0x8118, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x8118, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x8118, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "video_cc_mvs1_shift_clk", - .parent_hws = (const struct clk_hw*[]) { - &video_cc_xo_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct gdsc video_cc_mvs0c_gdsc = { - .gdscr = 0x8034, - .en_rest_wait_val = 0x2, - .en_few_wait_val = 0x2, - .clk_dis_wait_val = 0x6, - .pd = { - .name = "video_cc_mvs0c_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, -}; - -static struct gdsc video_cc_mvs0_gdsc = { - .gdscr = 0x8068, - .en_rest_wait_val = 0x2, - .en_few_wait_val = 0x2, - .clk_dis_wait_val = 0x6, - .pd = { - .name = "video_cc_mvs0_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .parent = &video_cc_mvs0c_gdsc.pd, - .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, -}; - -static struct gdsc video_cc_mvs1_gdsc = { - .gdscr = 0x80a4, - .en_rest_wait_val = 0x2, - .en_few_wait_val = 0x2, - .clk_dis_wait_val = 0x6, - .pd = { - .name = "video_cc_mvs1_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, -}; - -static struct clk_regmap *video_cc_nord_clocks[] = { - [VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr, - [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr, - [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr, - [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr, - [VIDEO_CC_MVS0_FREERUN_CLK] = &video_cc_mvs0_freerun_clk.clkr, - [VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr, - [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr, - [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr, - [VIDEO_CC_MVS0C_FREERUN_CLK] = &video_cc_mvs0c_freerun_clk.clkr, - [VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr, - [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr, - [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr, - [VIDEO_CC_MVS1_FREERUN_CLK] = &video_cc_mvs1_freerun_clk.clkr, - [VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr, - [VIDEO_CC_PLL0] = &video_cc_pll0.clkr, - [VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr, -}; - -static struct gdsc *video_cc_nord_gdscs[] = { - [VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc, - [VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc, - [VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc, -}; - -static const struct qcom_reset_map video_cc_nord_resets[] = { - [VIDEO_CC_INTERFACE_BCR] = { 0x80dc }, - [VIDEO_CC_MVS0_BCR] = { 0x8064 }, - [VIDEO_CC_MVS0C_CLK_ARES] = { 0x804c, 2 }, - [VIDEO_CC_MVS0C_BCR] = { 0x8030 }, - [VIDEO_CC_MVS1_BCR] = { 0x80a0 }, -}; - -static struct clk_alpha_pll *video_cc_nord_plls[] = { - &video_cc_pll0, -}; - -static const u32 video_cc_nord_critical_cbcrs[] = { - 0x80e0, /* VIDEO_CC_AHB_CLK */ - 0x8138, /* VIDEO_CC_SLEEP_CLK */ - 0x8110, /* VIDEO_CC_XO_CLK */ -}; - -static const struct regmap_config video_cc_nord_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0xa060, - .fast_io = true, -}; - -static void videocc_nord_regs_configure(struct device *dev, struct regmap *regmap) -{ - /* - * Enable clk_on sync for MVS0 and MVS0_FREERUN clocks via - * VIDEO_CC_SPARE1 during core reset by default. - */ - regmap_set_bits(regmap, 0x9f24, BIT(0)); -} - -static const struct qcom_cc_driver_data video_cc_nord_driver_data = { - .alpha_plls = video_cc_nord_plls, - .num_alpha_plls = ARRAY_SIZE(video_cc_nord_plls), - .clk_cbcrs = video_cc_nord_critical_cbcrs, - .num_clk_cbcrs = ARRAY_SIZE(video_cc_nord_critical_cbcrs), - .clk_regs_configure = videocc_nord_regs_configure, -}; - -static const struct qcom_cc_desc video_cc_nord_desc = { - .config = &video_cc_nord_regmap_config, - .clks = video_cc_nord_clocks, - .num_clks = ARRAY_SIZE(video_cc_nord_clocks), - .resets = video_cc_nord_resets, - .num_resets = ARRAY_SIZE(video_cc_nord_resets), - .gdscs = video_cc_nord_gdscs, - .num_gdscs = ARRAY_SIZE(video_cc_nord_gdscs), - .use_rpm = true, - .driver_data = &video_cc_nord_driver_data, -}; - -static const struct of_device_id video_cc_nord_match_table[] = { - { .compatible = "qcom,nord-videocc" }, - { } -}; -MODULE_DEVICE_TABLE(of, video_cc_nord_match_table); - -static int video_cc_nord_probe(struct platform_device *pdev) -{ - return qcom_cc_probe(pdev, &video_cc_nord_desc); -} - -static struct platform_driver video_cc_nord_driver = { - .probe = video_cc_nord_probe, - .driver = { - .name = "videocc-nord", - .of_match_table = video_cc_nord_match_table, - }, -}; - -module_platform_driver(video_cc_nord_driver); - -MODULE_DESCRIPTION("QTI VIDEOCC Nord Driver"); -MODULE_LICENSE("GPL"); From 4c2ed442a13481e77d97bf4beb412a1225d19c08 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 6 Aug 2026 12:24:03 +0530 Subject: [PATCH 04/11] Revert "FROMLIST: clk: qcom: camcc: Add support for camera clock controller for Nord" This reverts commit 7ab1c7c31badaadc79dc106f9774d6826be24072. Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 11 - drivers/clk/qcom/Makefile | 1 - drivers/clk/qcom/camcc-nord.c | 2941 --------------------------------- 3 files changed, 2953 deletions(-) delete mode 100644 drivers/clk/qcom/camcc-nord.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 36020b208734c..95d615ae9aef0 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -197,17 +197,6 @@ config CLK_KAANAPALI_VIDEOCC Say Y if you want to support video devices and functionality such as video encode/decode. -config CLK_NORD_CAMCC - tristate "Nord Camera Clock Controller" - depends on ARM64 || COMPILE_TEST - select CLK_NORD_GCC - default m if ARCH_QCOM - help - Support for the camera clock controller on Qualcomm Technologies, Inc - Nord devices. - Say Y if you want to support camera devices and functionality such as - capturing pictures. - config CLK_NORD_DISPCC tristate "Nord Display Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 5e0cbe4c09228..35eb04212e0c5 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -43,7 +43,6 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_GPUCC) += gpucc-kaanapali.o gxclkctl-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o -obj-$(CONFIG_CLK_NORD_CAMCC) += camcc-nord.o obj-$(CONFIG_CLK_NORD_DISPCC) += dispcc0-nord.o dispcc1-nord.o obj-$(CONFIG_CLK_NORD_GCC) += gcc-nord.o negcc-nord.o nwgcc-nord.o segcc-nord.o obj-$(CONFIG_CLK_NORD_GPUCC) += gpucc-nord.o gpu2cc-nord.o diff --git a/drivers/clk/qcom/camcc-nord.c b/drivers/clk/qcom/camcc-nord.c deleted file mode 100644 index 9e3c40cb3ad5f..0000000000000 --- a/drivers/clk/qcom/camcc-nord.c +++ /dev/null @@ -1,2941 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -#include -#include -#include -#include - -#include - -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "clk-regmap-divider.h" -#include "clk-regmap-mux.h" -#include "common.h" -#include "gdsc.h" -#include "reset.h" - -enum { - DT_IFACE, - DT_BI_TCXO, - DT_BI_TCXO_AO, - DT_SLEEP_CLK -}; - -enum { - P_BI_TCXO, - P_CAM_CC_PLL0_OUT_EVEN, - P_CAM_CC_PLL0_OUT_MAIN, - P_CAM_CC_PLL0_OUT_ODD, - P_CAM_CC_PLL2_OUT_EVEN, - P_CAM_CC_PLL3_OUT_EVEN, - P_CAM_CC_PLL4_OUT_EVEN, - P_CAM_CC_PLL5_OUT_EVEN, - P_CAM_CC_PLL6_OUT_EVEN, - P_SLEEP_CLK, -}; - -static const struct pll_vco lucid_ole_vco[] = { - { 249600000, 2300000000, 0 }, -}; - -/* 1200.0 MHz Configuration */ -static const struct alpha_pll_config cam_cc_pll0_config = { - .l = 0x3e, - .alpha = 0x8000, - .config_ctl_val = 0x20485699, - .config_ctl_hi_val = 0x00182261, - .config_ctl_hi1_val = 0x82aa299c, - .test_ctl_val = 0x00000000, - .test_ctl_hi_val = 0x00000003, - .test_ctl_hi1_val = 0x00009000, - .test_ctl_hi2_val = 0x00000034, - .user_ctl_val = 0x00008400, - .user_ctl_hi_val = 0x00400005, -}; - -static struct clk_alpha_pll cam_cc_pll0 = { - .offset = 0x0, - .config = &cam_cc_pll0_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr = { - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_pll0", - .parent_data = &(const struct clk_parent_data) { - .index = DT_BI_TCXO_AO, - }, - .num_parents = 1, - .ops = &clk_alpha_pll_lucid_evo_ops, - }, - }, -}; - -static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { - { 0x1, 2 }, - { } -}; - -static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { - .offset = 0x0, - .post_div_shift = 10, - .post_div_table = post_div_table_cam_cc_pll0_out_even, - .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), - .width = 4, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_pll0_out_even", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_pll0.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, - }, -}; - -static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { - { 0x2, 3 }, - { } -}; - -static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { - .offset = 0x0, - .post_div_shift = 14, - .post_div_table = post_div_table_cam_cc_pll0_out_odd, - .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), - .width = 4, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_pll0_out_odd", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_pll0.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, - }, -}; - -/* 720.0 MHz Configuration */ -static const struct alpha_pll_config cam_cc_pll2_config = { - .l = 0x25, - .alpha = 0x8000, - .config_ctl_val = 0x20485699, - .config_ctl_hi_val = 0x00182261, - .config_ctl_hi1_val = 0x82aa299c, - .test_ctl_val = 0x00000000, - .test_ctl_hi_val = 0x00000003, - .test_ctl_hi1_val = 0x00009000, - .test_ctl_hi2_val = 0x00000034, - .user_ctl_val = 0x00000400, - .user_ctl_hi_val = 0x00400005, -}; - -static struct clk_alpha_pll cam_cc_pll2 = { - .offset = 0x2000, - .config = &cam_cc_pll2_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr = { - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_pll2", - .parent_data = &(const struct clk_parent_data) { - .index = DT_BI_TCXO, - }, - .num_parents = 1, - .ops = &clk_alpha_pll_lucid_evo_ops, - }, - }, -}; - -static const struct clk_div_table post_div_table_cam_cc_pll2_out_even[] = { - { 0x1, 2 }, - { } -}; - -static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = { - .offset = 0x2000, - .post_div_shift = 10, - .post_div_table = post_div_table_cam_cc_pll2_out_even, - .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_even), - .width = 4, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_pll2_out_even", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_pll2.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, - }, -}; - -/* 720.0 MHz Configuration */ -static const struct alpha_pll_config cam_cc_pll3_config = { - .l = 0x25, - .alpha = 0x8000, - .config_ctl_val = 0x20485699, - .config_ctl_hi_val = 0x00182261, - .config_ctl_hi1_val = 0x82aa299c, - .test_ctl_val = 0x00000000, - .test_ctl_hi_val = 0x00000003, - .test_ctl_hi1_val = 0x00009000, - .test_ctl_hi2_val = 0x00000034, - .user_ctl_val = 0x00000400, - .user_ctl_hi_val = 0x00400005, -}; - -static struct clk_alpha_pll cam_cc_pll3 = { - .offset = 0x3000, - .config = &cam_cc_pll3_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr = { - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_pll3", - .parent_data = &(const struct clk_parent_data) { - .index = DT_BI_TCXO, - }, - .num_parents = 1, - .ops = &clk_alpha_pll_lucid_evo_ops, - }, - }, -}; - -static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { - { 0x1, 2 }, - { } -}; - -static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { - .offset = 0x3000, - .post_div_shift = 10, - .post_div_table = post_div_table_cam_cc_pll3_out_even, - .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), - .width = 4, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_pll3_out_even", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_pll3.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, - }, -}; - -/* 720.0 MHz Configuration */ -static const struct alpha_pll_config cam_cc_pll4_config = { - .l = 0x25, - .alpha = 0x8000, - .config_ctl_val = 0x20485699, - .config_ctl_hi_val = 0x00182261, - .config_ctl_hi1_val = 0x82aa299c, - .test_ctl_val = 0x00000000, - .test_ctl_hi_val = 0x00000003, - .test_ctl_hi1_val = 0x00009000, - .test_ctl_hi2_val = 0x00000034, - .user_ctl_val = 0x00000400, - .user_ctl_hi_val = 0x00400005, -}; - -static struct clk_alpha_pll cam_cc_pll4 = { - .offset = 0x4000, - .config = &cam_cc_pll4_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr = { - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_pll4", - .parent_data = &(const struct clk_parent_data) { - .index = DT_BI_TCXO, - }, - .num_parents = 1, - .ops = &clk_alpha_pll_lucid_evo_ops, - }, - }, -}; - -static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { - { 0x1, 2 }, - { } -}; - -static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { - .offset = 0x4000, - .post_div_shift = 10, - .post_div_table = post_div_table_cam_cc_pll4_out_even, - .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), - .width = 4, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_pll4_out_even", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_pll4.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, - }, -}; - -/* 720.0 MHz Configuration */ -static const struct alpha_pll_config cam_cc_pll5_config = { - .l = 0x25, - .alpha = 0x8000, - .config_ctl_val = 0x20485699, - .config_ctl_hi_val = 0x00182261, - .config_ctl_hi1_val = 0x82aa299c, - .test_ctl_val = 0x00000000, - .test_ctl_hi_val = 0x00000003, - .test_ctl_hi1_val = 0x00009000, - .test_ctl_hi2_val = 0x00000034, - .user_ctl_val = 0x00000400, - .user_ctl_hi_val = 0x00400005, -}; - -static struct clk_alpha_pll cam_cc_pll5 = { - .offset = 0x5000, - .config = &cam_cc_pll5_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr = { - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_pll5", - .parent_data = &(const struct clk_parent_data) { - .index = DT_BI_TCXO, - }, - .num_parents = 1, - .ops = &clk_alpha_pll_lucid_evo_ops, - }, - }, -}; - -static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { - { 0x1, 2 }, - { } -}; - -static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { - .offset = 0x5000, - .post_div_shift = 10, - .post_div_table = post_div_table_cam_cc_pll5_out_even, - .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), - .width = 4, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_pll5_out_even", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_pll5.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, - }, -}; - -/* 720.0 MHz Configuration */ -static const struct alpha_pll_config cam_cc_pll6_config = { - .l = 0x25, - .alpha = 0x8000, - .config_ctl_val = 0x20485699, - .config_ctl_hi_val = 0x00182261, - .config_ctl_hi1_val = 0x82aa299c, - .test_ctl_val = 0x00000000, - .test_ctl_hi_val = 0x00000003, - .test_ctl_hi1_val = 0x00009000, - .test_ctl_hi2_val = 0x00000034, - .user_ctl_val = 0x00000400, - .user_ctl_hi_val = 0x00400005, -}; - -static struct clk_alpha_pll cam_cc_pll6 = { - .offset = 0x6000, - .config = &cam_cc_pll6_config, - .vco_table = lucid_ole_vco, - .num_vco = ARRAY_SIZE(lucid_ole_vco), - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr = { - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_pll6", - .parent_data = &(const struct clk_parent_data) { - .index = DT_BI_TCXO, - }, - .num_parents = 1, - .ops = &clk_alpha_pll_lucid_evo_ops, - }, - }, -}; - -static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { - { 0x1, 2 }, - { } -}; - -static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { - .offset = 0x6000, - .post_div_shift = 10, - .post_div_table = post_div_table_cam_cc_pll6_out_even, - .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), - .width = 4, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_pll6_out_even", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_pll6.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, - }, -}; - -static const struct parent_map cam_cc_parent_map_0[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL0_OUT_MAIN, 1 }, - { P_CAM_CC_PLL0_OUT_EVEN, 2 }, - { P_CAM_CC_PLL0_OUT_ODD, 3 }, -}; - -static const struct clk_parent_data cam_cc_parent_data_0[] = { - { .index = DT_BI_TCXO }, - { .hw = &cam_cc_pll0.clkr.hw }, - { .hw = &cam_cc_pll0_out_even.clkr.hw }, - { .hw = &cam_cc_pll0_out_odd.clkr.hw }, -}; - -static const struct parent_map cam_cc_parent_map_1[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL0_OUT_MAIN, 1 }, - { P_CAM_CC_PLL0_OUT_EVEN, 2 }, - { P_CAM_CC_PLL0_OUT_ODD, 3 }, -}; - -static const struct clk_parent_data cam_cc_parent_data_1[] = { - { .index = DT_BI_TCXO }, - { .hw = &cam_cc_pll0.clkr.hw }, - { .hw = &cam_cc_pll0_out_even.clkr.hw }, - { .hw = &cam_cc_pll0_out_odd.clkr.hw }, -}; - -static const struct parent_map cam_cc_parent_map_2[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL0_OUT_MAIN, 1 }, - { P_CAM_CC_PLL0_OUT_EVEN, 2 }, - { P_CAM_CC_PLL3_OUT_EVEN, 3 }, -}; - -static const struct clk_parent_data cam_cc_parent_data_2[] = { - { .index = DT_BI_TCXO }, - { .hw = &cam_cc_pll0.clkr.hw }, - { .hw = &cam_cc_pll0_out_even.clkr.hw }, - { .hw = &cam_cc_pll3_out_even.clkr.hw }, -}; - -static const struct parent_map cam_cc_parent_map_3[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL2_OUT_EVEN, 2 }, -}; - -static const struct clk_parent_data cam_cc_parent_data_3[] = { - { .index = DT_BI_TCXO }, - { .hw = &cam_cc_pll2_out_even.clkr.hw }, -}; - -static const struct parent_map cam_cc_parent_map_4[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL4_OUT_EVEN, 6 }, -}; - -static const struct clk_parent_data cam_cc_parent_data_4[] = { - { .index = DT_BI_TCXO }, - { .hw = &cam_cc_pll4_out_even.clkr.hw }, -}; - -static const struct parent_map cam_cc_parent_map_5[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL5_OUT_EVEN, 6 }, -}; - -static const struct clk_parent_data cam_cc_parent_data_5[] = { - { .index = DT_BI_TCXO }, - { .hw = &cam_cc_pll5_out_even.clkr.hw }, -}; - -static const struct parent_map cam_cc_parent_map_6[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL6_OUT_EVEN, 6 }, -}; - -static const struct clk_parent_data cam_cc_parent_data_6[] = { - { .index = DT_BI_TCXO }, - { .hw = &cam_cc_pll6_out_even.clkr.hw }, -}; - -static const struct parent_map cam_cc_parent_map_7[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL0_OUT_MAIN, 1 }, - { P_CAM_CC_PLL0_OUT_EVEN, 2 }, -}; - -static const struct clk_parent_data cam_cc_parent_data_7[] = { - { .index = DT_BI_TCXO }, - { .hw = &cam_cc_pll0.clkr.hw }, - { .hw = &cam_cc_pll0_out_even.clkr.hw }, -}; - -static const struct parent_map cam_cc_parent_map_8[] = { - { P_SLEEP_CLK, 0 }, -}; - -static const struct clk_parent_data cam_cc_parent_data_8[] = { - { .index = DT_SLEEP_CLK }, -}; - -static const struct parent_map cam_cc_parent_map_9[] = { - { P_BI_TCXO, 0 }, -}; - -static const struct clk_parent_data cam_cc_parent_data_9[] = { - { .index = DT_BI_TCXO }, -}; - -static const struct freq_tbl ftbl_cam_cc_camnoc_rt_axi_clk_src[] = { - F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), - F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_camnoc_rt_axi_clk_src = { - .cmd_rcgr = 0x13244, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_camnoc_rt_axi_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_camnoc_rt_axi_clk_src", - .parent_data = cam_cc_parent_data_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { - F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_cci_0_clk_src = { - .cmd_rcgr = 0x13110, - .mnd_width = 8, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_cci_0_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_cci_0_clk_src", - .parent_data = cam_cc_parent_data_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 cam_cc_cci_1_clk_src = { - .cmd_rcgr = 0x13130, - .mnd_width = 8, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_cci_0_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_cci_1_clk_src", - .parent_data = cam_cc_parent_data_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 cam_cc_cci_2_clk_src = { - .cmd_rcgr = 0x13150, - .mnd_width = 8, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_cci_0_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_cci_2_clk_src", - .parent_data = cam_cc_parent_data_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 cam_cc_cci_3_clk_src = { - .cmd_rcgr = 0x13170, - .mnd_width = 8, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_cci_0_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_cci_3_clk_src", - .parent_data = cam_cc_parent_data_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 cam_cc_cci_4_clk_src = { - .cmd_rcgr = 0x13190, - .mnd_width = 8, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_cci_0_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_cci_4_clk_src", - .parent_data = cam_cc_parent_data_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { - F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), - F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), - F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { - .cmd_rcgr = 0x120ac, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_cphy_rx_clk_src", - .parent_data = cam_cc_parent_data_1, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { - F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), - F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { - .cmd_rcgr = 0x10000, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csi0phytimer_clk_src", - .parent_data = cam_cc_parent_data_1, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { - .cmd_rcgr = 0x10028, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csi1phytimer_clk_src", - .parent_data = cam_cc_parent_data_1, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { - .cmd_rcgr = 0x1004c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csi2phytimer_clk_src", - .parent_data = cam_cc_parent_data_1, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { - .cmd_rcgr = 0x10070, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csi3phytimer_clk_src", - .parent_data = cam_cc_parent_data_1, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { - .cmd_rcgr = 0x10094, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csi4phytimer_clk_src", - .parent_data = cam_cc_parent_data_1, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = { - F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), - F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), - F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_csid_clk_src = { - .cmd_rcgr = 0x13214, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_csid_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csid_clk_src", - .parent_data = cam_cc_parent_data_1, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { - F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), - F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), - F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { - .cmd_rcgr = 0x131dc, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_fast_ahb_clk_src", - .parent_data = cam_cc_parent_data_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_icp_0_clk_src[] = { - F(360000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), - F(480000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), - F(600000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_icp_0_clk_src = { - .cmd_rcgr = 0x130a4, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_2, - .freq_tbl = ftbl_cam_cc_icp_0_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_icp_0_clk_src", - .parent_data = cam_cc_parent_data_2, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 cam_cc_icp_1_clk_src = { - .cmd_rcgr = 0x130dc, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_2, - .freq_tbl = ftbl_cam_cc_icp_0_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_icp_1_clk_src", - .parent_data = cam_cc_parent_data_2, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_ife_0_main_clk_src[] = { - F(360000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), - F(480000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), - F(650000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_ife_0_main_clk_src = { - .cmd_rcgr = 0x12018, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_4, - .freq_tbl = ftbl_cam_cc_ife_0_main_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_0_main_clk_src", - .parent_data = cam_cc_parent_data_4, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_ife_1_main_clk_src[] = { - F(360000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), - F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), - F(650000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_ife_1_main_clk_src = { - .cmd_rcgr = 0x120dc, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_5, - .freq_tbl = ftbl_cam_cc_ife_1_main_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_1_main_clk_src", - .parent_data = cam_cc_parent_data_5, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_ife_2_main_clk_src[] = { - F(360000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), - F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), - F(650000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_ife_2_main_clk_src = { - .cmd_rcgr = 0x12188, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_6, - .freq_tbl = ftbl_cam_cc_ife_2_main_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_2_main_clk_src", - .parent_data = cam_cc_parent_data_6, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 cam_cc_ife_lite_clk_src = { - .cmd_rcgr = 0x13000, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_csid_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_lite_clk_src", - .parent_data = cam_cc_parent_data_1, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { - .cmd_rcgr = 0x13024, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_csid_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_lite_csid_clk_src", - .parent_data = cam_cc_parent_data_1, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { - F(360000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), - F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), - F(650000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_ipe_0_clk_src = { - .cmd_rcgr = 0x11018, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_3, - .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ipe_0_clk_src", - .parent_data = cam_cc_parent_data_3, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 cam_cc_ipe_1_clk_src = { - .cmd_rcgr = 0x11074, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_3, - .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ipe_1_clk_src", - .parent_data = cam_cc_parent_data_3, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { - F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), - F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { - .cmd_rcgr = 0x13330, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_qdss_debug_clk_src", - .parent_data = cam_cc_parent_data_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_qup_ahbm_clk_src[] = { - F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), - F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_qup_ahbm_clk_src = { - .cmd_rcgr = 0x132e8, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_qup_ahbm_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_qup_ahbm_clk_src", - .parent_data = cam_cc_parent_data_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_qup_core_2x_clk_src[] = { - F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), - F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_qup_core_2x_clk_src = { - .cmd_rcgr = 0x132a0, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_qup_core_2x_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_qup_core_2x_clk_src", - .parent_data = cam_cc_parent_data_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_rcg2 cam_cc_qup_se_clk_src = { - .cmd_rcgr = 0x13308, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_7, - .freq_tbl = ftbl_cam_cc_cci_0_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_qup_se_clk_src", - .parent_data = cam_cc_parent_data_7, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { - F(32000, P_SLEEP_CLK, 1, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_sleep_clk_src = { - .cmd_rcgr = 0x13384, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_8, - .freq_tbl = ftbl_cam_cc_sleep_clk_src, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_sleep_clk_src", - .parent_data = cam_cc_parent_data_8, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_8), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { - F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { - .cmd_rcgr = 0x131f8, - .mnd_width = 8, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_slow_ahb_clk_src", - .parent_data = cam_cc_parent_data_0, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_xo_clk_src = { - .cmd_rcgr = 0x13368, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_9, - .freq_tbl = ftbl_cam_cc_xo_clk_src, - .hw_clk_ctrl = true, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_xo_clk_src", - .parent_data = cam_cc_parent_data_9, - .num_parents = ARRAY_SIZE(cam_cc_parent_data_9), - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_shared_ops, - }, -}; - -static struct clk_regmap_div cam_cc_qup_core_2x_div_clk_src = { - .reg = 0x132cc, - .shift = 0, - .width = 4, - .clkr.hw.init = &(const struct clk_init_data) { - .name = "cam_cc_qup_core_2x_div_clk_src", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_qup_core_2x_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_regmap_div_ro_ops, - }, -}; - -static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { - .halt_reg = 0x13290, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x13290, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_camnoc_dcd_xo_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_xo_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_camnoc_nrt_axi_clk = { - .halt_reg = 0x13278, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x13278, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_camnoc_nrt_axi_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_camnoc_rt_axi_clk = { - .halt_reg = 0x13260, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x13260, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_camnoc_rt_axi_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_cci_0_clk = { - .halt_reg = 0x1312c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1312c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_cci_0_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_cci_0_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_cci_1_clk = { - .halt_reg = 0x1314c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1314c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_cci_1_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_cci_1_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_cci_2_clk = { - .halt_reg = 0x1316c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1316c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_cci_2_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_cci_2_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_cci_3_clk = { - .halt_reg = 0x1318c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1318c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_cci_3_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_cci_3_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_cci_4_clk = { - .halt_reg = 0x131ac, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x131ac, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_cci_4_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_cci_4_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ccu_fast_ahb_clk = { - .halt_reg = 0x1329c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1329c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ccu_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csi0phytimer_clk = { - .halt_reg = 0x1001c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1001c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csi0phytimer_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_csi0phytimer_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csi1phytimer_clk = { - .halt_reg = 0x10044, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10044, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csi1phytimer_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_csi1phytimer_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csi2phytimer_clk = { - .halt_reg = 0x10068, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10068, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csi2phytimer_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_csi2phytimer_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csi3phytimer_clk = { - .halt_reg = 0x1008c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1008c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csi3phytimer_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_csi3phytimer_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csi4phytimer_clk = { - .halt_reg = 0x100b0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x100b0, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csi4phytimer_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_csi4phytimer_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csid_clk = { - .halt_reg = 0x13230, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x13230, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csid_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_csid_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csid_csiphy_rx_clk = { - .halt_reg = 0x10024, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10024, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csid_csiphy_rx_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_cphy_rx_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csiphy0_clk = { - .halt_reg = 0x10020, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10020, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csiphy0_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_cphy_rx_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csiphy1_clk = { - .halt_reg = 0x10048, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10048, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csiphy1_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_cphy_rx_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csiphy2_clk = { - .halt_reg = 0x1006c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1006c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csiphy2_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_cphy_rx_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csiphy3_clk = { - .halt_reg = 0x10090, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10090, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csiphy3_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_cphy_rx_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csiphy4_clk = { - .halt_reg = 0x100b4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x100b4, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_csiphy4_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_cphy_rx_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_icp_0_ahb_clk = { - .halt_reg = 0x130d4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x130d4, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_icp_0_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_slow_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_icp_0_clk = { - .halt_reg = 0x130c0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x130c0, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_icp_0_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_icp_0_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_icp_1_ahb_clk = { - .halt_reg = 0x1310c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1310c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_icp_1_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_slow_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_icp_1_clk = { - .halt_reg = 0x130f8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x130f8, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_icp_1_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_icp_1_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_0_main_clk = { - .halt_reg = 0x12034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x12034, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_0_main_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_0_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_0_main_fast_ahb_clk = { - .halt_reg = 0x12054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x12054, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_0_main_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_0_pcp_clk = { - .halt_reg = 0x12058, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x12058, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_0_pcp_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_0_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_0_pcp_fast_ahb_clk = { - .halt_reg = 0x12070, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x12070, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_0_pcp_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_0_scalar_clk = { - .halt_reg = 0x12074, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x12074, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_0_scalar_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_0_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_0_scalar_fast_ahb_clk = { - .halt_reg = 0x1208c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1208c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_0_scalar_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_0_tmc_clk = { - .halt_reg = 0x12090, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x12090, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_0_tmc_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_0_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_0_tmc_fast_ahb_clk = { - .halt_reg = 0x120a8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x120a8, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_0_tmc_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_1_main_clk = { - .halt_reg = 0x120f8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x120f8, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_1_main_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_1_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_1_main_fast_ahb_clk = { - .halt_reg = 0x12118, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x12118, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_1_main_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_1_pcp_clk = { - .halt_reg = 0x1211c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1211c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_1_pcp_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_1_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_1_pcp_fast_ahb_clk = { - .halt_reg = 0x12134, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x12134, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_1_pcp_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_1_scalar_clk = { - .halt_reg = 0x12138, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x12138, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_1_scalar_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_1_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_1_scalar_fast_ahb_clk = { - .halt_reg = 0x12150, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x12150, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_1_scalar_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_1_tmc_clk = { - .halt_reg = 0x12154, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x12154, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_1_tmc_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_1_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_1_tmc_fast_ahb_clk = { - .halt_reg = 0x1216c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1216c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_1_tmc_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_2_main_clk = { - .halt_reg = 0x121a4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x121a4, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_2_main_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_2_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_2_main_fast_ahb_clk = { - .halt_reg = 0x121c4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x121c4, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_2_main_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_2_pcp_clk = { - .halt_reg = 0x121c8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x121c8, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_2_pcp_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_2_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_2_pcp_fast_ahb_clk = { - .halt_reg = 0x121e0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x121e0, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_2_pcp_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_2_scalar_clk = { - .halt_reg = 0x121e4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x121e4, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_2_scalar_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_2_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_2_scalar_fast_ahb_clk = { - .halt_reg = 0x121fc, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x121fc, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_2_scalar_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_2_tmc_clk = { - .halt_reg = 0x12200, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x12200, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_2_tmc_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_2_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_2_tmc_fast_ahb_clk = { - .halt_reg = 0x12218, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x12218, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_2_tmc_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_lite_ahb_clk = { - .halt_reg = 0x13054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x13054, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_lite_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_slow_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_lite_clk = { - .halt_reg = 0x1301c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1301c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_lite_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_lite_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { - .halt_reg = 0x13050, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x13050, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_lite_cphy_rx_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_cphy_rx_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_lite_csid_clk = { - .halt_reg = 0x1303c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1303c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ife_lite_csid_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_lite_csid_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ipe_0_ahb_clk = { - .halt_reg = 0x11054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x11054, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ipe_0_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_slow_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ipe_0_clk = { - .halt_reg = 0x11034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x11034, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ipe_0_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ipe_0_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ipe_0_fast_ahb_clk = { - .halt_reg = 0x11058, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x11058, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ipe_0_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ipe_1_ahb_clk = { - .halt_reg = 0x110b0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x110b0, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ipe_1_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_slow_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ipe_1_clk = { - .halt_reg = 0x11090, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x11090, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ipe_1_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ipe_1_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ipe_1_fast_ahb_clk = { - .halt_reg = 0x110b4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x110b4, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_ipe_1_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_qdss_debug_clk = { - .halt_reg = 0x13348, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x13348, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_qdss_debug_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_qdss_debug_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_qdss_debug_xo_clk = { - .halt_reg = 0x1334c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1334c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_qdss_debug_xo_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_xo_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_qup_ahbm_clk = { - .halt_reg = 0x13300, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x13300, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_qup_ahbm_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_qup_ahbm_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_qup_core_2x_clk = { - .halt_reg = 0x132b8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x132b8, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_qup_core_2x_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_qup_core_2x_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_qup_core_clk = { - .halt_reg = 0x132d0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x132d0, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_qup_core_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_qup_core_2x_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_qup_se_clk = { - .halt_reg = 0x13320, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x13320, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_qup_se_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_qup_se_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_sfe_lite_0_clk = { - .halt_reg = 0x1305c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1305c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_sfe_lite_0_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_0_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_sfe_lite_0_fast_ahb_clk = { - .halt_reg = 0x1306c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1306c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_sfe_lite_0_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_sfe_lite_1_clk = { - .halt_reg = 0x13074, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x13074, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_sfe_lite_1_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_1_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_sfe_lite_1_fast_ahb_clk = { - .halt_reg = 0x13084, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x13084, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_sfe_lite_1_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_sfe_lite_2_clk = { - .halt_reg = 0x1308c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1308c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_sfe_lite_2_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_2_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_sfe_lite_2_fast_ahb_clk = { - .halt_reg = 0x1309c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1309c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_sfe_lite_2_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_sm_obs_clk = { - .halt_reg = 0x1401c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1401c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_sm_obs_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_top_ahb_clk = { - .halt_reg = 0x131b0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x131b0, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_top_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_slow_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_top_fast_ahb_clk = { - .halt_reg = 0x131c4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x131c4, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_top_fast_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_fast_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_top_ife_0_clk = { - .halt_reg = 0x12048, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x12048, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_top_ife_0_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_0_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_top_ife_1_clk = { - .halt_reg = 0x1210c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1210c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_top_ife_1_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_1_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_top_ife_2_clk = { - .halt_reg = 0x121b8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x121b8, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_top_ife_2_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_2_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_top_ife_lite_clk = { - .halt_reg = 0x13020, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x13020, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_top_ife_lite_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_lite_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_top_ipe_0_clk = { - .halt_reg = 0x11048, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x11048, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_top_ipe_0_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ipe_0_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_top_ipe_1_clk = { - .halt_reg = 0x110a4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x110a4, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_top_ipe_1_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ipe_1_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_top_qup_ahbm_clk = { - .halt_reg = 0x13304, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x13304, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_top_qup_ahbm_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_qup_ahbm_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_top_sfe_lite_0_clk = { - .halt_reg = 0x13060, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x13060, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_top_sfe_lite_0_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_0_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_top_sfe_lite_1_clk = { - .halt_reg = 0x13078, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x13078, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_top_sfe_lite_1_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_1_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_top_sfe_lite_2_clk = { - .halt_reg = 0x13090, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x13090, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_top_sfe_lite_2_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_ife_2_main_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_tpg_csiphy_rx_clk = { - .halt_reg = 0x100b8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x100b8, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "cam_cc_tpg_csiphy_rx_clk", - .parent_hws = (const struct clk_hw*[]) { - &cam_cc_cphy_rx_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct gdsc cam_cc_titan_top_gdsc = { - .gdscr = 0x13350, - .en_rest_wait_val = 0x2, - .en_few_wait_val = 0x2, - .clk_dis_wait_val = 0xf, - .pd = { - .name = "cam_cc_titan_top_gdsc", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, -}; - -static struct gdsc cam_cc_ife_0_gdsc = { - .gdscr = 0x12004, - .en_rest_wait_val = 0x2, - .en_few_wait_val = 0x2, - .clk_dis_wait_val = 0xf, - .pd = { - .name = "cam_cc_ife_0_gdsc", - }, - .parent = &cam_cc_titan_top_gdsc.pd, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, -}; - -static struct gdsc cam_cc_ife_1_gdsc = { - .gdscr = 0x120c8, - .en_rest_wait_val = 0x2, - .en_few_wait_val = 0x2, - .clk_dis_wait_val = 0xf, - .pd = { - .name = "cam_cc_ife_1_gdsc", - }, - .parent = &cam_cc_titan_top_gdsc.pd, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, -}; - -static struct gdsc cam_cc_ife_2_gdsc = { - .gdscr = 0x12174, - .en_rest_wait_val = 0x2, - .en_few_wait_val = 0x2, - .clk_dis_wait_val = 0xf, - .pd = { - .name = "cam_cc_ife_2_gdsc", - }, - .parent = &cam_cc_titan_top_gdsc.pd, - .pwrsts = PWRSTS_OFF_ON, - .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, -}; - -static struct gdsc cam_cc_ipe_0_gdsc = { - .gdscr = 0x11004, - .en_rest_wait_val = 0x2, - .en_few_wait_val = 0x2, - .clk_dis_wait_val = 0xf, - .pd = { - .name = "cam_cc_ipe_0_gdsc", - }, - .parent = &cam_cc_titan_top_gdsc.pd, - .pwrsts = PWRSTS_OFF_ON, - .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, -}; - -static struct gdsc cam_cc_ipe_1_gdsc = { - .gdscr = 0x11060, - .en_rest_wait_val = 0x2, - .en_few_wait_val = 0x2, - .clk_dis_wait_val = 0xf, - .pd = { - .name = "cam_cc_ipe_1_gdsc", - }, - .parent = &cam_cc_titan_top_gdsc.pd, - .pwrsts = PWRSTS_OFF_ON, - .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, -}; - -static struct clk_regmap *cam_cc_nord_clocks[] = { - [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, - [CAM_CC_CAMNOC_NRT_AXI_CLK] = &cam_cc_camnoc_nrt_axi_clk.clkr, - [CAM_CC_CAMNOC_RT_AXI_CLK] = &cam_cc_camnoc_rt_axi_clk.clkr, - [CAM_CC_CAMNOC_RT_AXI_CLK_SRC] = &cam_cc_camnoc_rt_axi_clk_src.clkr, - [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, - [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, - [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, - [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, - [CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr, - [CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr, - [CAM_CC_CCI_3_CLK] = &cam_cc_cci_3_clk.clkr, - [CAM_CC_CCI_3_CLK_SRC] = &cam_cc_cci_3_clk_src.clkr, - [CAM_CC_CCI_4_CLK] = &cam_cc_cci_4_clk.clkr, - [CAM_CC_CCI_4_CLK_SRC] = &cam_cc_cci_4_clk_src.clkr, - [CAM_CC_CCU_FAST_AHB_CLK] = &cam_cc_ccu_fast_ahb_clk.clkr, - [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, - [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, - [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, - [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, - [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, - [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, - [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, - [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, - [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, - [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, - [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, - [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, - [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, - [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, - [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, - [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, - [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, - [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, - [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, - [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, - [CAM_CC_ICP_0_AHB_CLK] = &cam_cc_icp_0_ahb_clk.clkr, - [CAM_CC_ICP_0_CLK] = &cam_cc_icp_0_clk.clkr, - [CAM_CC_ICP_0_CLK_SRC] = &cam_cc_icp_0_clk_src.clkr, - [CAM_CC_ICP_1_AHB_CLK] = &cam_cc_icp_1_ahb_clk.clkr, - [CAM_CC_ICP_1_CLK] = &cam_cc_icp_1_clk.clkr, - [CAM_CC_ICP_1_CLK_SRC] = &cam_cc_icp_1_clk_src.clkr, - [CAM_CC_IFE_0_MAIN_CLK] = &cam_cc_ife_0_main_clk.clkr, - [CAM_CC_IFE_0_MAIN_CLK_SRC] = &cam_cc_ife_0_main_clk_src.clkr, - [CAM_CC_IFE_0_MAIN_FAST_AHB_CLK] = &cam_cc_ife_0_main_fast_ahb_clk.clkr, - [CAM_CC_IFE_0_PCP_CLK] = &cam_cc_ife_0_pcp_clk.clkr, - [CAM_CC_IFE_0_PCP_FAST_AHB_CLK] = &cam_cc_ife_0_pcp_fast_ahb_clk.clkr, - [CAM_CC_IFE_0_SCALAR_CLK] = &cam_cc_ife_0_scalar_clk.clkr, - [CAM_CC_IFE_0_SCALAR_FAST_AHB_CLK] = &cam_cc_ife_0_scalar_fast_ahb_clk.clkr, - [CAM_CC_IFE_0_TMC_CLK] = &cam_cc_ife_0_tmc_clk.clkr, - [CAM_CC_IFE_0_TMC_FAST_AHB_CLK] = &cam_cc_ife_0_tmc_fast_ahb_clk.clkr, - [CAM_CC_IFE_1_MAIN_CLK] = &cam_cc_ife_1_main_clk.clkr, - [CAM_CC_IFE_1_MAIN_CLK_SRC] = &cam_cc_ife_1_main_clk_src.clkr, - [CAM_CC_IFE_1_MAIN_FAST_AHB_CLK] = &cam_cc_ife_1_main_fast_ahb_clk.clkr, - [CAM_CC_IFE_1_PCP_CLK] = &cam_cc_ife_1_pcp_clk.clkr, - [CAM_CC_IFE_1_PCP_FAST_AHB_CLK] = &cam_cc_ife_1_pcp_fast_ahb_clk.clkr, - [CAM_CC_IFE_1_SCALAR_CLK] = &cam_cc_ife_1_scalar_clk.clkr, - [CAM_CC_IFE_1_SCALAR_FAST_AHB_CLK] = &cam_cc_ife_1_scalar_fast_ahb_clk.clkr, - [CAM_CC_IFE_1_TMC_CLK] = &cam_cc_ife_1_tmc_clk.clkr, - [CAM_CC_IFE_1_TMC_FAST_AHB_CLK] = &cam_cc_ife_1_tmc_fast_ahb_clk.clkr, - [CAM_CC_IFE_2_MAIN_CLK] = &cam_cc_ife_2_main_clk.clkr, - [CAM_CC_IFE_2_MAIN_CLK_SRC] = &cam_cc_ife_2_main_clk_src.clkr, - [CAM_CC_IFE_2_MAIN_FAST_AHB_CLK] = &cam_cc_ife_2_main_fast_ahb_clk.clkr, - [CAM_CC_IFE_2_PCP_CLK] = &cam_cc_ife_2_pcp_clk.clkr, - [CAM_CC_IFE_2_PCP_FAST_AHB_CLK] = &cam_cc_ife_2_pcp_fast_ahb_clk.clkr, - [CAM_CC_IFE_2_SCALAR_CLK] = &cam_cc_ife_2_scalar_clk.clkr, - [CAM_CC_IFE_2_SCALAR_FAST_AHB_CLK] = &cam_cc_ife_2_scalar_fast_ahb_clk.clkr, - [CAM_CC_IFE_2_TMC_CLK] = &cam_cc_ife_2_tmc_clk.clkr, - [CAM_CC_IFE_2_TMC_FAST_AHB_CLK] = &cam_cc_ife_2_tmc_fast_ahb_clk.clkr, - [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, - [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, - [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, - [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, - [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, - [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, - [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, - [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, - [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, - [CAM_CC_IPE_0_FAST_AHB_CLK] = &cam_cc_ipe_0_fast_ahb_clk.clkr, - [CAM_CC_IPE_1_AHB_CLK] = &cam_cc_ipe_1_ahb_clk.clkr, - [CAM_CC_IPE_1_CLK] = &cam_cc_ipe_1_clk.clkr, - [CAM_CC_IPE_1_CLK_SRC] = &cam_cc_ipe_1_clk_src.clkr, - [CAM_CC_IPE_1_FAST_AHB_CLK] = &cam_cc_ipe_1_fast_ahb_clk.clkr, - [CAM_CC_PLL0] = &cam_cc_pll0.clkr, - [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, - [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, - [CAM_CC_PLL2] = &cam_cc_pll2.clkr, - [CAM_CC_PLL2_OUT_EVEN] = &cam_cc_pll2_out_even.clkr, - [CAM_CC_PLL3] = &cam_cc_pll3.clkr, - [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, - [CAM_CC_PLL4] = &cam_cc_pll4.clkr, - [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, - [CAM_CC_PLL5] = &cam_cc_pll5.clkr, - [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, - [CAM_CC_PLL6] = &cam_cc_pll6.clkr, - [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, - [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, - [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, - [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, - [CAM_CC_QUP_AHBM_CLK] = &cam_cc_qup_ahbm_clk.clkr, - [CAM_CC_QUP_AHBM_CLK_SRC] = &cam_cc_qup_ahbm_clk_src.clkr, - [CAM_CC_QUP_CORE_2X_CLK] = &cam_cc_qup_core_2x_clk.clkr, - [CAM_CC_QUP_CORE_2X_CLK_SRC] = &cam_cc_qup_core_2x_clk_src.clkr, - [CAM_CC_QUP_CORE_2X_DIV_CLK_SRC] = &cam_cc_qup_core_2x_div_clk_src.clkr, - [CAM_CC_QUP_CORE_CLK] = &cam_cc_qup_core_clk.clkr, - [CAM_CC_QUP_SE_CLK] = &cam_cc_qup_se_clk.clkr, - [CAM_CC_QUP_SE_CLK_SRC] = &cam_cc_qup_se_clk_src.clkr, - [CAM_CC_SFE_LITE_0_CLK] = &cam_cc_sfe_lite_0_clk.clkr, - [CAM_CC_SFE_LITE_0_FAST_AHB_CLK] = &cam_cc_sfe_lite_0_fast_ahb_clk.clkr, - [CAM_CC_SFE_LITE_1_CLK] = &cam_cc_sfe_lite_1_clk.clkr, - [CAM_CC_SFE_LITE_1_FAST_AHB_CLK] = &cam_cc_sfe_lite_1_fast_ahb_clk.clkr, - [CAM_CC_SFE_LITE_2_CLK] = &cam_cc_sfe_lite_2_clk.clkr, - [CAM_CC_SFE_LITE_2_FAST_AHB_CLK] = &cam_cc_sfe_lite_2_fast_ahb_clk.clkr, - [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, - [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, - [CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr, - [CAM_CC_TOP_AHB_CLK] = &cam_cc_top_ahb_clk.clkr, - [CAM_CC_TOP_FAST_AHB_CLK] = &cam_cc_top_fast_ahb_clk.clkr, - [CAM_CC_TOP_IFE_0_CLK] = &cam_cc_top_ife_0_clk.clkr, - [CAM_CC_TOP_IFE_1_CLK] = &cam_cc_top_ife_1_clk.clkr, - [CAM_CC_TOP_IFE_2_CLK] = &cam_cc_top_ife_2_clk.clkr, - [CAM_CC_TOP_IFE_LITE_CLK] = &cam_cc_top_ife_lite_clk.clkr, - [CAM_CC_TOP_IPE_0_CLK] = &cam_cc_top_ipe_0_clk.clkr, - [CAM_CC_TOP_IPE_1_CLK] = &cam_cc_top_ipe_1_clk.clkr, - [CAM_CC_TOP_QUP_AHBM_CLK] = &cam_cc_top_qup_ahbm_clk.clkr, - [CAM_CC_TOP_SFE_LITE_0_CLK] = &cam_cc_top_sfe_lite_0_clk.clkr, - [CAM_CC_TOP_SFE_LITE_1_CLK] = &cam_cc_top_sfe_lite_1_clk.clkr, - [CAM_CC_TOP_SFE_LITE_2_CLK] = &cam_cc_top_sfe_lite_2_clk.clkr, - [CAM_CC_TPG_CSIPHY_RX_CLK] = &cam_cc_tpg_csiphy_rx_clk.clkr, - [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, -}; - -static struct gdsc *cam_cc_nord_gdscs[] = { - [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, - [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc, - [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc, - [CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc, - [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, - [CAM_CC_IPE_1_GDSC] = &cam_cc_ipe_1_gdsc, -}; - -static const struct qcom_reset_map cam_cc_nord_resets[] = { - [CAM_CC_CCU_BCR] = { 0x13298 }, - [CAM_CC_ICP_0_BCR] = { 0x130a0 }, - [CAM_CC_ICP_1_BCR] = { 0x130d8 }, - [CAM_CC_IFE_0_BCR] = { 0x12000 }, - [CAM_CC_IFE_1_BCR] = { 0x120c4 }, - [CAM_CC_IFE_2_BCR] = { 0x12170 }, - [CAM_CC_IPE_0_BCR] = { 0x11000 }, - [CAM_CC_IPE_1_BCR] = { 0x1105c }, - [CAM_CC_QDSS_DEBUG_BCR] = { 0x1332c }, - [CAM_CC_SFE_LITE_0_BCR] = { 0x13058 }, - [CAM_CC_SFE_LITE_1_BCR] = { 0x13070 }, - [CAM_CC_SFE_LITE_2_BCR] = { 0x13088 }, -}; - -static struct clk_alpha_pll *cam_cc_nord_plls[] = { - &cam_cc_pll0, - &cam_cc_pll2, - &cam_cc_pll3, - &cam_cc_pll4, - &cam_cc_pll5, - &cam_cc_pll6, -}; - -static const u32 cam_cc_nord_critical_cbcrs[] = { - 0x13294, /* CAM_CC_CAMNOC_XO_CLK */ - 0x13364, /* CAM_CC_CORE_AHB_CLK */ - 0x13380, /* CAM_CC_GDSC_CLK */ - 0x132e4, /* CAM_CC_QUP_SLEEP_CLK */ - 0x1339c, /* CAM_CC_SLEEP_CLK */ -}; - -static const struct regmap_config cam_cc_nord_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x17000, - .fast_io = true, -}; - -static const struct qcom_cc_driver_data cam_cc_nord_driver_data = { - .alpha_plls = cam_cc_nord_plls, - .num_alpha_plls = ARRAY_SIZE(cam_cc_nord_plls), - .clk_cbcrs = cam_cc_nord_critical_cbcrs, - .num_clk_cbcrs = ARRAY_SIZE(cam_cc_nord_critical_cbcrs), -}; - -static const struct qcom_cc_desc cam_cc_nord_desc = { - .config = &cam_cc_nord_regmap_config, - .clks = cam_cc_nord_clocks, - .num_clks = ARRAY_SIZE(cam_cc_nord_clocks), - .resets = cam_cc_nord_resets, - .num_resets = ARRAY_SIZE(cam_cc_nord_resets), - .gdscs = cam_cc_nord_gdscs, - .num_gdscs = ARRAY_SIZE(cam_cc_nord_gdscs), - .use_rpm = true, - .driver_data = &cam_cc_nord_driver_data, -}; - -static const struct of_device_id cam_cc_nord_match_table[] = { - { .compatible = "qcom,nord-camcc" }, - { } -}; -MODULE_DEVICE_TABLE(of, cam_cc_nord_match_table); - -static int cam_cc_nord_probe(struct platform_device *pdev) -{ - return qcom_cc_probe(pdev, &cam_cc_nord_desc); -} - -static struct platform_driver cam_cc_nord_driver = { - .probe = cam_cc_nord_probe, - .driver = { - .name = "camcc-nord", - .of_match_table = cam_cc_nord_match_table, - }, -}; - -module_platform_driver(cam_cc_nord_driver); - -MODULE_DESCRIPTION("QTI CAMCC Nord Driver"); -MODULE_LICENSE("GPL"); From a9b02f8460367ec0118f7ebc7b3488e2dc95f4d5 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sat, 1 Aug 2026 19:43:52 +0530 Subject: [PATCH 05/11] dt-bindings: clock: qcom: Add GCC video axi reset clocks for Nord The NW_GCC video axi reset clocks are required by the video SW driver to assert and deassert the clock resets during their power down sequence. Hence add these clock resets. Fixes: 06498d59bb4e ("dt-bindings: clock: qcom: Add Nord Global Clock Controller") Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-1-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das --- include/dt-bindings/clock/qcom,nord-nwgcc.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/qcom,nord-nwgcc.h b/include/dt-bindings/clock/qcom,nord-nwgcc.h index b6253dd2aa85a..8beaa129aa814 100644 --- a/include/dt-bindings/clock/qcom,nord-nwgcc.h +++ b/include/dt-bindings/clock/qcom,nord-nwgcc.h @@ -65,5 +65,8 @@ #define NW_GCC_GPU_2_BCR 6 #define NW_GCC_GPU_BCR 7 #define NW_GCC_VIDEO_BCR 8 +#define NW_GCC_VIDEO_AXI0_CLK_ARES 9 +#define NW_GCC_VIDEO_AXI0C_CLK_ARES 10 +#define NW_GCC_VIDEO_AXI1_CLK_ARES 11 #endif From d2bcedcc53bc6930e1148e668f4185e7a3434039 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sat, 1 Aug 2026 19:43:53 +0530 Subject: [PATCH 06/11] clk: qcom: nwgcc-nord: Add video axi clock resets for Nord The global clock controller video axi reset clocks are required by the video SW driver to assert and deassert the clock resets during their power down sequence. Hence add these clock resets. Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC") Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-2-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das --- drivers/clk/qcom/nwgcc-nord.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/nwgcc-nord.c b/drivers/clk/qcom/nwgcc-nord.c index e061c0623e9a4..280558f15748c 100644 --- a/drivers/clk/qcom/nwgcc-nord.c +++ b/drivers/clk/qcom/nwgcc-nord.c @@ -623,6 +623,9 @@ static const struct qcom_reset_map nw_gcc_nord_resets[] = { [NW_GCC_GPU_2_BCR] = { 0x24000 }, [NW_GCC_GPU_BCR] = { 0x23000 }, [NW_GCC_VIDEO_BCR] = { 0x1a000 }, + [NW_GCC_VIDEO_AXI0_CLK_ARES] = { 0x1a008, 2 }, + [NW_GCC_VIDEO_AXI0C_CLK_ARES] = { 0x1a01c, 2 }, + [NW_GCC_VIDEO_AXI1_CLK_ARES] = { 0x1a030, 2 }, }; static const u32 nw_gcc_nord_critical_cbcrs[] = { From 1bfa8a669dd6ab66a69a510a9ea68cde0a59e1d8 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 6 Aug 2026 16:08:23 +0530 Subject: [PATCH 07/11] dt-bindings: clock: qcom: Add video clock controller on Nord SoC Add compatible string for Nord video clock controller and the bindings for Nord Qualcomm SoC. Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-3-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das --- .../devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index 5d77029bfaf88..9b9878e9b9cfc 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -17,6 +17,7 @@ description: | See also: include/dt-bindings/clock/qcom,glymur-videocc.h include/dt-bindings/clock/qcom,kaanapali-videocc.h + include/dt-bindings/clock/qcom,nord-videocc.h include/dt-bindings/clock/qcom,sm8450-videocc.h include/dt-bindings/clock/qcom,sm8650-videocc.h include/dt-bindings/clock/qcom,sm8750-videocc.h @@ -27,6 +28,7 @@ properties: enum: - qcom,glymur-videocc - qcom,kaanapali-videocc + - qcom,nord-videocc - qcom,sm8450-videocc - qcom,sm8475-videocc - qcom,sm8550-videocc From 841bc14c4a5c386fe65e1e017b2e7efb95a83420 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sat, 1 Aug 2026 19:43:55 +0530 Subject: [PATCH 08/11] dt-bindings: clock: qcom: Add support for Camera Clock Controller for Nord Update the compatible and the bindings for CAMCC support on Nord SoC. Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-4-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sm8450-camcc.yaml | 2 + include/dt-bindings/clock/qcom,nord-camcc.h | 167 ++++++++++++++++++ 2 files changed, 169 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,nord-camcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index 8492a7ef73245..8e460df9f7444 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -18,6 +18,7 @@ description: | See also: include/dt-bindings/clock/qcom,kaanapali-camcc.h include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h + include/dt-bindings/clock/qcom,nord-camcc.h include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h include/dt-bindings/clock/qcom,sm8650-camcc.h @@ -29,6 +30,7 @@ properties: enum: - qcom,kaanapali-cambistmclkcc - qcom,kaanapali-camcc + - qcom,nord-camcc - qcom,sm8450-camcc - qcom,sm8475-camcc - qcom,sm8550-camcc diff --git a/include/dt-bindings/clock/qcom,nord-camcc.h b/include/dt-bindings/clock/qcom,nord-camcc.h new file mode 100644 index 0000000000000..655fef2084a58 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-camcc.h @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_NORD_H + +/* CAM_CC clocks */ +#define CAM_CC_CAMNOC_DCD_XO_CLK 0 +#define CAM_CC_CAMNOC_NRT_AXI_CLK 1 +#define CAM_CC_CAMNOC_RT_AXI_CLK 2 +#define CAM_CC_CAMNOC_RT_AXI_CLK_SRC 3 +#define CAM_CC_CAMNOC_XO_CLK 4 +#define CAM_CC_CCI_0_CLK 5 +#define CAM_CC_CCI_0_CLK_SRC 6 +#define CAM_CC_CCI_1_CLK 7 +#define CAM_CC_CCI_1_CLK_SRC 8 +#define CAM_CC_CCI_2_CLK 9 +#define CAM_CC_CCI_2_CLK_SRC 10 +#define CAM_CC_CCI_3_CLK 11 +#define CAM_CC_CCI_3_CLK_SRC 12 +#define CAM_CC_CCI_4_CLK 13 +#define CAM_CC_CCI_4_CLK_SRC 14 +#define CAM_CC_CCU_FAST_AHB_CLK 15 +#define CAM_CC_CORE_AHB_CLK 16 +#define CAM_CC_CPHY_RX_CLK_SRC 17 +#define CAM_CC_CSI0PHYTIMER_CLK 18 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 19 +#define CAM_CC_CSI1PHYTIMER_CLK 20 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 21 +#define CAM_CC_CSI2PHYTIMER_CLK 22 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 23 +#define CAM_CC_CSI3PHYTIMER_CLK 24 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 25 +#define CAM_CC_CSI4PHYTIMER_CLK 26 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 27 +#define CAM_CC_CSID_CLK 28 +#define CAM_CC_CSID_CLK_SRC 29 +#define CAM_CC_CSID_CSIPHY_RX_CLK 30 +#define CAM_CC_CSIPHY0_CLK 31 +#define CAM_CC_CSIPHY1_CLK 32 +#define CAM_CC_CSIPHY2_CLK 33 +#define CAM_CC_CSIPHY3_CLK 34 +#define CAM_CC_CSIPHY4_CLK 35 +#define CAM_CC_FAST_AHB_CLK_SRC 36 +#define CAM_CC_GDSC_CLK 37 +#define CAM_CC_ICP_0_AHB_CLK 38 +#define CAM_CC_ICP_0_CLK 39 +#define CAM_CC_ICP_0_CLK_SRC 40 +#define CAM_CC_ICP_1_AHB_CLK 41 +#define CAM_CC_ICP_1_CLK 42 +#define CAM_CC_ICP_1_CLK_SRC 43 +#define CAM_CC_IFE_0_MAIN_CLK 44 +#define CAM_CC_IFE_0_MAIN_CLK_SRC 45 +#define CAM_CC_IFE_0_MAIN_FAST_AHB_CLK 46 +#define CAM_CC_IFE_0_PCP_CLK 47 +#define CAM_CC_IFE_0_PCP_FAST_AHB_CLK 48 +#define CAM_CC_IFE_0_SCALAR_CLK 49 +#define CAM_CC_IFE_0_SCALAR_FAST_AHB_CLK 50 +#define CAM_CC_IFE_0_TMC_CLK 51 +#define CAM_CC_IFE_0_TMC_FAST_AHB_CLK 52 +#define CAM_CC_IFE_1_MAIN_CLK 53 +#define CAM_CC_IFE_1_MAIN_CLK_SRC 54 +#define CAM_CC_IFE_1_MAIN_FAST_AHB_CLK 55 +#define CAM_CC_IFE_1_PCP_CLK 56 +#define CAM_CC_IFE_1_PCP_FAST_AHB_CLK 57 +#define CAM_CC_IFE_1_SCALAR_CLK 58 +#define CAM_CC_IFE_1_SCALAR_FAST_AHB_CLK 59 +#define CAM_CC_IFE_1_TMC_CLK 60 +#define CAM_CC_IFE_1_TMC_FAST_AHB_CLK 61 +#define CAM_CC_IFE_2_MAIN_CLK 62 +#define CAM_CC_IFE_2_MAIN_CLK_SRC 63 +#define CAM_CC_IFE_2_MAIN_FAST_AHB_CLK 64 +#define CAM_CC_IFE_2_PCP_CLK 65 +#define CAM_CC_IFE_2_PCP_FAST_AHB_CLK 66 +#define CAM_CC_IFE_2_SCALAR_CLK 67 +#define CAM_CC_IFE_2_SCALAR_FAST_AHB_CLK 68 +#define CAM_CC_IFE_2_TMC_CLK 69 +#define CAM_CC_IFE_2_TMC_FAST_AHB_CLK 70 +#define CAM_CC_IFE_LITE_AHB_CLK 71 +#define CAM_CC_IFE_LITE_CLK 72 +#define CAM_CC_IFE_LITE_CLK_SRC 73 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 74 +#define CAM_CC_IFE_LITE_CSID_CLK 75 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 76 +#define CAM_CC_IPE_0_AHB_CLK 77 +#define CAM_CC_IPE_0_CLK 78 +#define CAM_CC_IPE_0_CLK_SRC 79 +#define CAM_CC_IPE_0_FAST_AHB_CLK 80 +#define CAM_CC_IPE_1_AHB_CLK 81 +#define CAM_CC_IPE_1_CLK 82 +#define CAM_CC_IPE_1_CLK_SRC 83 +#define CAM_CC_IPE_1_FAST_AHB_CLK 84 +#define CAM_CC_PLL0 85 +#define CAM_CC_PLL0_OUT_EVEN 86 +#define CAM_CC_PLL0_OUT_ODD 87 +#define CAM_CC_PLL2 88 +#define CAM_CC_PLL2_OUT_EVEN 89 +#define CAM_CC_PLL3 90 +#define CAM_CC_PLL3_OUT_EVEN 91 +#define CAM_CC_PLL4 92 +#define CAM_CC_PLL4_OUT_EVEN 93 +#define CAM_CC_PLL5 94 +#define CAM_CC_PLL5_OUT_EVEN 95 +#define CAM_CC_PLL6 96 +#define CAM_CC_PLL6_OUT_EVEN 97 +#define CAM_CC_QDSS_DEBUG_CLK 98 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 99 +#define CAM_CC_QDSS_DEBUG_XO_CLK 100 +#define CAM_CC_QUP_AHBM_CLK 101 +#define CAM_CC_QUP_AHBM_CLK_SRC 102 +#define CAM_CC_QUP_CORE_2X_CLK 103 +#define CAM_CC_QUP_CORE_2X_CLK_SRC 104 +#define CAM_CC_QUP_CORE_2X_DIV_CLK_SRC 105 +#define CAM_CC_QUP_CORE_CLK 106 +#define CAM_CC_QUP_SE_CLK 107 +#define CAM_CC_QUP_SE_CLK_SRC 108 +#define CAM_CC_QUP_SLEEP_CLK 109 +#define CAM_CC_SFE_LITE_0_CLK 110 +#define CAM_CC_SFE_LITE_0_FAST_AHB_CLK 111 +#define CAM_CC_SFE_LITE_1_CLK 112 +#define CAM_CC_SFE_LITE_1_FAST_AHB_CLK 113 +#define CAM_CC_SFE_LITE_2_CLK 114 +#define CAM_CC_SFE_LITE_2_FAST_AHB_CLK 115 +#define CAM_CC_SLEEP_CLK 116 +#define CAM_CC_SLEEP_CLK_SRC 117 +#define CAM_CC_SLOW_AHB_CLK_SRC 118 +#define CAM_CC_SM_OBS_CLK 119 +#define CAM_CC_TOP_AHB_CLK 120 +#define CAM_CC_TOP_FAST_AHB_CLK 121 +#define CAM_CC_TOP_IFE_0_CLK 122 +#define CAM_CC_TOP_IFE_1_CLK 123 +#define CAM_CC_TOP_IFE_2_CLK 124 +#define CAM_CC_TOP_IFE_LITE_CLK 125 +#define CAM_CC_TOP_IPE_0_CLK 126 +#define CAM_CC_TOP_IPE_1_CLK 127 +#define CAM_CC_TOP_QUP_AHBM_CLK 128 +#define CAM_CC_TOP_SFE_LITE_0_CLK 129 +#define CAM_CC_TOP_SFE_LITE_1_CLK 130 +#define CAM_CC_TOP_SFE_LITE_2_CLK 131 +#define CAM_CC_TPG_CSIPHY_RX_CLK 132 +#define CAM_CC_XO_CLK_SRC 133 + +/* CAM_CC power domains */ +#define CAM_CC_IFE_0_GDSC 0 +#define CAM_CC_IFE_1_GDSC 1 +#define CAM_CC_IFE_2_GDSC 2 +#define CAM_CC_IPE_0_GDSC 3 +#define CAM_CC_IPE_1_GDSC 4 +#define CAM_CC_TITAN_TOP_GDSC 5 + +/* CAM_CC resets */ +#define CAM_CC_CCU_BCR 0 +#define CAM_CC_ICP_0_BCR 1 +#define CAM_CC_ICP_1_BCR 2 +#define CAM_CC_IFE_0_BCR 3 +#define CAM_CC_IFE_1_BCR 4 +#define CAM_CC_IFE_2_BCR 5 +#define CAM_CC_IPE_0_BCR 6 +#define CAM_CC_IPE_1_BCR 7 +#define CAM_CC_QDSS_DEBUG_BCR 8 +#define CAM_CC_SFE_LITE_0_BCR 9 +#define CAM_CC_SFE_LITE_1_BCR 10 +#define CAM_CC_SFE_LITE_2_BCR 11 + +#endif From 929c190f65dc730b107bf137173cd3f8fb6e3a40 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 6 Aug 2026 15:59:36 +0530 Subject: [PATCH 09/11] clk: qcom: videocc-glymur: Add video clock controller support for Nord Nord shares the video clock controller topology with Glymur, differing only in the PLL0 hardware (Lucid-OLE vs Taycan-EKO-T) and the MVS0 frequency table. Extend the existing Glymur video clock controller driver to also probe on the qcom,nord-videocc compatible, switching to the Nord PLL configuration, VCO table, and MVS0 frequency table at probe time. Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-5-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 11 +++++++++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-glymur.c | 38 +++++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 95d615ae9aef0..6eca90433ca5a 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -240,6 +240,17 @@ config CLK_SHIKRA_AUDIOCORECC Say Y if you want to use AudioCoreCC clocks required to support audio devices and it's functionality. +config CLK_NORD_VIDEOCC + tristate "Nord VIDEO Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_NORD_GCC + default m if ARCH_QCOM + help + Support for the video clock controller on Qualcomm Technologies, Inc. + Nord devices. + Say Y if you want to support video devices and functionality such as + video encode/decode. + config CLK_SHIKRA_GCC tristate "Shikra Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 35eb04212e0c5..4353923b2558b 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_CLK_NORD_DISPCC) += dispcc0-nord.o dispcc1-nord.o obj-$(CONFIG_CLK_NORD_GCC) += gcc-nord.o negcc-nord.o nwgcc-nord.o segcc-nord.o obj-$(CONFIG_CLK_NORD_GPUCC) += gpucc-nord.o gpu2cc-nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o +obj-$(CONFIG_CLK_NORD_VIDEOCC) += videocc-glymur.o obj-$(CONFIG_CLK_SHIKRA_AUDIOCORECC) += audiocorecc-shikra.o obj-$(CONFIG_CLK_SHIKRA_GCC) += gcc-shikra.o obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o diff --git a/drivers/clk/qcom/videocc-glymur.c b/drivers/clk/qcom/videocc-glymur.c index 18313a65e78d9..2776140de3555 100644 --- a/drivers/clk/qcom/videocc-glymur.c +++ b/drivers/clk/qcom/videocc-glymur.c @@ -37,6 +37,10 @@ static const struct pll_vco taycan_eko_t_vco[] = { { 249600000, 2500000000, 0 }, }; +static const struct pll_vco lucid_ole_vco[] = { + { 249600000, 2300000000, 0 }, +}; + /* 720.0 MHz Configuration */ static const struct alpha_pll_config video_cc_pll0_config = { .l = 0x25, @@ -48,6 +52,21 @@ static const struct alpha_pll_config video_cc_pll0_config = { .user_ctl_hi_val = 0x00000002, }; +/* 720.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll0_config_nord = { + .l = 0x25, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000000, + .user_ctl_hi_val = 0x00400005, +}; + static struct clk_alpha_pll video_cc_pll0 = { .offset = 0x0, .config = &video_cc_pll0_config, @@ -112,6 +131,15 @@ static struct clk_rcg2 video_cc_ahb_clk_src = { }, }; +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_nord[] = { + F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1305000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1440000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1680000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), @@ -508,12 +536,22 @@ static const struct qcom_cc_desc video_cc_glymur_desc = { static const struct of_device_id video_cc_glymur_match_table[] = { { .compatible = "qcom,glymur-videocc" }, + { .compatible = "qcom,nord-videocc" }, { } }; MODULE_DEVICE_TABLE(of, video_cc_glymur_match_table); static int video_cc_glymur_probe(struct platform_device *pdev) { + if (of_device_is_compatible(pdev->dev.of_node, "qcom,nord-videocc")) { + video_cc_pll0.vco_table = lucid_ole_vco; + video_cc_pll0.num_vco = ARRAY_SIZE(lucid_ole_vco); + video_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + video_cc_pll0.config = &video_cc_pll0_config_nord; + + video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_nord; + } + return qcom_cc_probe(pdev, &video_cc_glymur_desc); } From 85188bc48698bcb207a9708710001e6eee2044d8 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 6 Aug 2026 16:01:46 +0530 Subject: [PATCH 10/11] clk: qcom: camcc: Add support for camera clock controller for Nord Add support for the Camera Clock Controller (CAMCC) on the Nord platform for camera SW drivers to request for these clocks. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-6-674d7718e41f@oss.qualcomm.com Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/camcc-nord.c | 2941 +++++++++++++++++++++++++++++++++ 3 files changed, 2953 insertions(+) create mode 100644 drivers/clk/qcom/camcc-nord.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 6eca90433ca5a..0173a712c1231 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -208,6 +208,17 @@ config CLK_NORD_DISPCC Say Y if you want to support display devices and functionality such as splash screen. +config CLK_NORD_CAMCC + tristate "Nord Camera Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_NORD_GCC + default m if ARCH_QCOM + help + Support for the camera clock controller on Qualcomm Technologies, Inc + Nord devices. + Say Y if you want to support camera devices and functionality such as + capturing pictures. + config CLK_NORD_GCC tristate "Nord Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 4353923b2558b..3489b6dc1d55f 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_GPUCC) += gpucc-kaanapali.o gxclkctl-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o +obj-$(CONFIG_CLK_NORD_CAMCC) += camcc-nord.o obj-$(CONFIG_CLK_NORD_DISPCC) += dispcc0-nord.o dispcc1-nord.o obj-$(CONFIG_CLK_NORD_GCC) += gcc-nord.o negcc-nord.o nwgcc-nord.o segcc-nord.o obj-$(CONFIG_CLK_NORD_GPUCC) += gpucc-nord.o gpu2cc-nord.o diff --git a/drivers/clk/qcom/camcc-nord.c b/drivers/clk/qcom/camcc-nord.c new file mode 100644 index 0000000000000..9e3c40cb3ad5f --- /dev/null +++ b/drivers/clk/qcom/camcc-nord.c @@ -0,0 +1,2941 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_IFACE, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK +}; + +enum { + P_BI_TCXO, + P_CAM_CC_PLL0_OUT_EVEN, + P_CAM_CC_PLL0_OUT_MAIN, + P_CAM_CC_PLL0_OUT_ODD, + P_CAM_CC_PLL2_OUT_EVEN, + P_CAM_CC_PLL3_OUT_EVEN, + P_CAM_CC_PLL4_OUT_EVEN, + P_CAM_CC_PLL5_OUT_EVEN, + P_CAM_CC_PLL6_OUT_EVEN, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_ole_vco[] = { + { 249600000, 2300000000, 0 }, +}; + +/* 1200.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll0_config = { + .l = 0x3e, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00008400, + .user_ctl_hi_val = 0x00400005, +}; + +static struct clk_alpha_pll cam_cc_pll0 = { + .offset = 0x0, + .config = &cam_cc_pll0_config, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO_AO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { + .offset = 0x0, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { + .offset = 0x0, + .post_div_shift = 14, + .post_div_table = post_div_table_cam_cc_pll0_out_odd, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0_out_odd", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +/* 720.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll2_config = { + .l = 0x25, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00400005, +}; + +static struct clk_alpha_pll cam_cc_pll2 = { + .offset = 0x2000, + .config = &cam_cc_pll2_config, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll2", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll2_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = { + .offset = 0x2000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll2_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll2_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll2.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +/* 720.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll3_config = { + .l = 0x25, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00400005, +}; + +static struct clk_alpha_pll cam_cc_pll3 = { + .offset = 0x3000, + .config = &cam_cc_pll3_config, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll3", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { + .offset = 0x3000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll3_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll3_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll3.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +/* 720.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll4_config = { + .l = 0x25, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00400005, +}; + +static struct clk_alpha_pll cam_cc_pll4 = { + .offset = 0x4000, + .config = &cam_cc_pll4_config, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll4", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { + .offset = 0x4000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll4_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll4_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll4.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +/* 720.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll5_config = { + .l = 0x25, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00400005, +}; + +static struct clk_alpha_pll cam_cc_pll5 = { + .offset = 0x5000, + .config = &cam_cc_pll5_config, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll5", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { + .offset = 0x5000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll5_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll5_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll5.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +/* 720.0 MHz Configuration */ +static const struct alpha_pll_config cam_cc_pll6_config = { + .l = 0x25, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00400005, +}; + +static struct clk_alpha_pll cam_cc_pll6 = { + .offset = 0x6000, + .config = &cam_cc_pll6_config, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll6", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { + .offset = 0x6000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll6_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll6_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll6.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_evo_ops, + }, +}; + +static const struct parent_map cam_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll0.clkr.hw }, + { .hw = &cam_cc_pll0_out_even.clkr.hw }, + { .hw = &cam_cc_pll0_out_odd.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll0.clkr.hw }, + { .hw = &cam_cc_pll0_out_even.clkr.hw }, + { .hw = &cam_cc_pll0_out_odd.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL3_OUT_EVEN, 3 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll0.clkr.hw }, + { .hw = &cam_cc_pll0_out_even.clkr.hw }, + { .hw = &cam_cc_pll3_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EVEN, 2 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll2_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL4_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_4[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll4_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL5_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_5[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll5_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_6[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL6_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_6[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll6_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_7[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_7[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll0.clkr.hw }, + { .hw = &cam_cc_pll0_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_8[] = { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_8[] = { + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map cam_cc_parent_map_9[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_9[] = { + { .index = DT_BI_TCXO }, +}; + +static const struct freq_tbl ftbl_cam_cc_camnoc_rt_axi_clk_src[] = { + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_camnoc_rt_axi_clk_src = { + .cmd_rcgr = 0x13244, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_camnoc_rt_axi_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_rt_axi_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { + F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cci_0_clk_src = { + .cmd_rcgr = 0x13110, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_0_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_1_clk_src = { + .cmd_rcgr = 0x13130, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_1_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_2_clk_src = { + .cmd_rcgr = 0x13150, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_2_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_3_clk_src = { + .cmd_rcgr = 0x13170, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_3_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_4_clk_src = { + .cmd_rcgr = 0x13190, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_4_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { + .cmd_rcgr = 0x120ac, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cphy_rx_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { + .cmd_rcgr = 0x10000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi0phytimer_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { + .cmd_rcgr = 0x10028, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi1phytimer_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { + .cmd_rcgr = 0x1004c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi2phytimer_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { + .cmd_rcgr = 0x10070, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi3phytimer_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { + .cmd_rcgr = 0x10094, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi4phytimer_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = { + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csid_clk_src = { + .cmd_rcgr = 0x13214, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_csid_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { + F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { + .cmd_rcgr = 0x131dc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_fast_ahb_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_icp_0_clk_src[] = { + F(360000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_icp_0_clk_src = { + .cmd_rcgr = 0x130a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_2, + .freq_tbl = ftbl_cam_cc_icp_0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_0_clk_src", + .parent_data = cam_cc_parent_data_2, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_icp_1_clk_src = { + .cmd_rcgr = 0x130dc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_2, + .freq_tbl = ftbl_cam_cc_icp_0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_1_clk_src", + .parent_data = cam_cc_parent_data_2, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_0_main_clk_src[] = { + F(360000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(650000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_0_main_clk_src = { + .cmd_rcgr = 0x12018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_4, + .freq_tbl = ftbl_cam_cc_ife_0_main_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_main_clk_src", + .parent_data = cam_cc_parent_data_4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_1_main_clk_src[] = { + F(360000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(650000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_1_main_clk_src = { + .cmd_rcgr = 0x120dc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_5, + .freq_tbl = ftbl_cam_cc_ife_1_main_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_main_clk_src", + .parent_data = cam_cc_parent_data_5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_2_main_clk_src[] = { + F(360000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(650000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_2_main_clk_src = { + .cmd_rcgr = 0x12188, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_6, + .freq_tbl = ftbl_cam_cc_ife_2_main_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_main_clk_src", + .parent_data = cam_cc_parent_data_6, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_clk_src = { + .cmd_rcgr = 0x13000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_csid_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { + .cmd_rcgr = 0x13024, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_csid_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_csid_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { + F(360000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + F(650000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ipe_0_clk_src = { + .cmd_rcgr = 0x11018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_3, + .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_0_clk_src", + .parent_data = cam_cc_parent_data_3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ipe_1_clk_src = { + .cmd_rcgr = 0x11074, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_3, + .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_1_clk_src", + .parent_data = cam_cc_parent_data_3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { + F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { + .cmd_rcgr = 0x13330, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_qup_ahbm_clk_src[] = { + F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), + F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qup_ahbm_clk_src = { + .cmd_rcgr = 0x132e8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_qup_ahbm_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qup_ahbm_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_qup_core_2x_clk_src[] = { + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qup_core_2x_clk_src = { + .cmd_rcgr = 0x132a0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_qup_core_2x_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qup_core_2x_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_qup_se_clk_src = { + .cmd_rcgr = 0x13308, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_7, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qup_se_clk_src", + .parent_data = cam_cc_parent_data_7, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sleep_clk_src = { + .cmd_rcgr = 0x13384, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_8, + .freq_tbl = ftbl_cam_cc_sleep_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sleep_clk_src", + .parent_data = cam_cc_parent_data_8, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_8), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { + .cmd_rcgr = 0x131f8, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_slow_ahb_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_xo_clk_src = { + .cmd_rcgr = 0x13368, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_9, + .freq_tbl = ftbl_cam_cc_xo_clk_src, + .hw_clk_ctrl = true, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_xo_clk_src", + .parent_data = cam_cc_parent_data_9, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_9), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div cam_cc_qup_core_2x_div_clk_src = { + .reg = 0x132cc, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qup_core_2x_div_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_qup_core_2x_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { + .halt_reg = 0x13290, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13290, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_dcd_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_nrt_axi_clk = { + .halt_reg = 0x13278, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13278, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_nrt_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_rt_axi_clk = { + .halt_reg = 0x13260, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13260, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_rt_axi_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_camnoc_rt_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_0_clk = { + .halt_reg = 0x1312c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1312c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_1_clk = { + .halt_reg = 0x1314c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1314c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_2_clk = { + .halt_reg = 0x1316c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1316c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_3_clk = { + .halt_reg = 0x1318c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1318c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_3_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_4_clk = { + .halt_reg = 0x131ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x131ac, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_4_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ccu_fast_ahb_clk = { + .halt_reg = 0x1329c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1329c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ccu_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi0phytimer_clk = { + .halt_reg = 0x1001c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1001c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi0phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi0phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi1phytimer_clk = { + .halt_reg = 0x10044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10044, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi1phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi1phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi2phytimer_clk = { + .halt_reg = 0x10068, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10068, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi2phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi2phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi3phytimer_clk = { + .halt_reg = 0x1008c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1008c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi3phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi3phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi4phytimer_clk = { + .halt_reg = 0x100b0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100b0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi4phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi4phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_clk = { + .halt_reg = 0x13230, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13230, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_csiphy_rx_clk = { + .halt_reg = 0x10024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10024, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_csiphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy0_clk = { + .halt_reg = 0x10020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10020, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy1_clk = { + .halt_reg = 0x10048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy2_clk = { + .halt_reg = 0x1006c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1006c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy3_clk = { + .halt_reg = 0x10090, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10090, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy3_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy4_clk = { + .halt_reg = 0x100b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100b4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy4_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_0_ahb_clk = { + .halt_reg = 0x130d4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130d4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_0_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_0_clk = { + .halt_reg = 0x130c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130c0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_icp_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_1_ahb_clk = { + .halt_reg = 0x1310c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1310c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_1_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_1_clk = { + .halt_reg = 0x130f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130f8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_icp_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_main_clk = { + .halt_reg = 0x12034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_main_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_main_fast_ahb_clk = { + .halt_reg = 0x12054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_main_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_pcp_clk = { + .halt_reg = 0x12058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12058, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_pcp_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_pcp_fast_ahb_clk = { + .halt_reg = 0x12070, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12070, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_pcp_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_scalar_clk = { + .halt_reg = 0x12074, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12074, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_scalar_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_scalar_fast_ahb_clk = { + .halt_reg = 0x1208c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1208c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_scalar_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_tmc_clk = { + .halt_reg = 0x12090, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12090, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_tmc_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_tmc_fast_ahb_clk = { + .halt_reg = 0x120a8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x120a8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_tmc_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_main_clk = { + .halt_reg = 0x120f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x120f8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_main_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_1_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_main_fast_ahb_clk = { + .halt_reg = 0x12118, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12118, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_main_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_pcp_clk = { + .halt_reg = 0x1211c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1211c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_pcp_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_1_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_pcp_fast_ahb_clk = { + .halt_reg = 0x12134, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12134, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_pcp_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_scalar_clk = { + .halt_reg = 0x12138, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12138, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_scalar_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_1_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_scalar_fast_ahb_clk = { + .halt_reg = 0x12150, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12150, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_scalar_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_tmc_clk = { + .halt_reg = 0x12154, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12154, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_tmc_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_1_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_tmc_fast_ahb_clk = { + .halt_reg = 0x1216c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1216c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_tmc_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_main_clk = { + .halt_reg = 0x121a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x121a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_main_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_2_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_main_fast_ahb_clk = { + .halt_reg = 0x121c4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x121c4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_main_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_pcp_clk = { + .halt_reg = 0x121c8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x121c8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_pcp_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_2_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_pcp_fast_ahb_clk = { + .halt_reg = 0x121e0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x121e0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_pcp_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_scalar_clk = { + .halt_reg = 0x121e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x121e4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_scalar_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_2_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_scalar_fast_ahb_clk = { + .halt_reg = 0x121fc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x121fc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_scalar_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_tmc_clk = { + .halt_reg = 0x12200, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12200, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_tmc_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_2_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_tmc_fast_ahb_clk = { + .halt_reg = 0x12218, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12218, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_tmc_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_ahb_clk = { + .halt_reg = 0x13054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_clk = { + .halt_reg = 0x1301c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1301c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { + .halt_reg = 0x13050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_cphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_csid_clk = { + .halt_reg = 0x1303c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1303c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_0_ahb_clk = { + .halt_reg = 0x11054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11054, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_0_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_0_clk = { + .halt_reg = 0x11034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_0_fast_ahb_clk = { + .halt_reg = 0x11058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11058, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_0_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_1_ahb_clk = { + .halt_reg = 0x110b0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x110b0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_1_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_1_clk = { + .halt_reg = 0x11090, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11090, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_1_fast_ahb_clk = { + .halt_reg = 0x110b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x110b4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_1_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_clk = { + .halt_reg = 0x13348, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13348, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_qdss_debug_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_xo_clk = { + .halt_reg = 0x1334c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1334c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qup_ahbm_clk = { + .halt_reg = 0x13300, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13300, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qup_ahbm_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_qup_ahbm_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qup_core_2x_clk = { + .halt_reg = 0x132b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x132b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qup_core_2x_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_qup_core_2x_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qup_core_clk = { + .halt_reg = 0x132d0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x132d0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qup_core_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_qup_core_2x_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qup_se_clk = { + .halt_reg = 0x13320, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13320, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qup_se_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_qup_se_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_lite_0_clk = { + .halt_reg = 0x1305c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1305c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_lite_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_lite_0_fast_ahb_clk = { + .halt_reg = 0x1306c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1306c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_lite_0_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_lite_1_clk = { + .halt_reg = 0x13074, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13074, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_lite_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_1_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_lite_1_fast_ahb_clk = { + .halt_reg = 0x13084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13084, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_lite_1_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_lite_2_clk = { + .halt_reg = 0x1308c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1308c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_lite_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_2_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_lite_2_fast_ahb_clk = { + .halt_reg = 0x1309c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1309c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_lite_2_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sm_obs_clk = { + .halt_reg = 0x1401c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1401c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sm_obs_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_ahb_clk = { + .halt_reg = 0x131b0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x131b0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_top_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_fast_ahb_clk = { + .halt_reg = 0x131c4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x131c4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_top_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_ife_0_clk = { + .halt_reg = 0x12048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_top_ife_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_ife_1_clk = { + .halt_reg = 0x1210c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1210c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_top_ife_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_1_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_ife_2_clk = { + .halt_reg = 0x121b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x121b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_top_ife_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_2_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_ife_lite_clk = { + .halt_reg = 0x13020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13020, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_top_ife_lite_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_ipe_0_clk = { + .halt_reg = 0x11048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_top_ipe_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_ipe_1_clk = { + .halt_reg = 0x110a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x110a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_top_ipe_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_qup_ahbm_clk = { + .halt_reg = 0x13304, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13304, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_top_qup_ahbm_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_qup_ahbm_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_sfe_lite_0_clk = { + .halt_reg = 0x13060, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13060, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_top_sfe_lite_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_sfe_lite_1_clk = { + .halt_reg = 0x13078, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13078, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_top_sfe_lite_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_1_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_top_sfe_lite_2_clk = { + .halt_reg = 0x13090, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13090, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_top_sfe_lite_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_2_main_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_tpg_csiphy_rx_clk = { + .halt_reg = 0x100b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_tpg_csiphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc cam_cc_titan_top_gdsc = { + .gdscr = 0x13350, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_titan_top_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_0_gdsc = { + .gdscr = 0x12004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ife_0_gdsc", + }, + .parent = &cam_cc_titan_top_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_1_gdsc = { + .gdscr = 0x120c8, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ife_1_gdsc", + }, + .parent = &cam_cc_titan_top_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_2_gdsc = { + .gdscr = 0x12174, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ife_2_gdsc", + }, + .parent = &cam_cc_titan_top_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ipe_0_gdsc = { + .gdscr = 0x11004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ipe_0_gdsc", + }, + .parent = &cam_cc_titan_top_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ipe_1_gdsc = { + .gdscr = 0x11060, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ipe_1_gdsc", + }, + .parent = &cam_cc_titan_top_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *cam_cc_nord_clocks[] = { + [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, + [CAM_CC_CAMNOC_NRT_AXI_CLK] = &cam_cc_camnoc_nrt_axi_clk.clkr, + [CAM_CC_CAMNOC_RT_AXI_CLK] = &cam_cc_camnoc_rt_axi_clk.clkr, + [CAM_CC_CAMNOC_RT_AXI_CLK_SRC] = &cam_cc_camnoc_rt_axi_clk_src.clkr, + [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, + [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, + [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, + [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, + [CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr, + [CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr, + [CAM_CC_CCI_3_CLK] = &cam_cc_cci_3_clk.clkr, + [CAM_CC_CCI_3_CLK_SRC] = &cam_cc_cci_3_clk_src.clkr, + [CAM_CC_CCI_4_CLK] = &cam_cc_cci_4_clk.clkr, + [CAM_CC_CCI_4_CLK_SRC] = &cam_cc_cci_4_clk_src.clkr, + [CAM_CC_CCU_FAST_AHB_CLK] = &cam_cc_ccu_fast_ahb_clk.clkr, + [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, + [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, + [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, + [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, + [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, + [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, + [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, + [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, + [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, + [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, + [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, + [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, + [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, + [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, + [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, + [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, + [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, + [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, + [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, + [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, + [CAM_CC_ICP_0_AHB_CLK] = &cam_cc_icp_0_ahb_clk.clkr, + [CAM_CC_ICP_0_CLK] = &cam_cc_icp_0_clk.clkr, + [CAM_CC_ICP_0_CLK_SRC] = &cam_cc_icp_0_clk_src.clkr, + [CAM_CC_ICP_1_AHB_CLK] = &cam_cc_icp_1_ahb_clk.clkr, + [CAM_CC_ICP_1_CLK] = &cam_cc_icp_1_clk.clkr, + [CAM_CC_ICP_1_CLK_SRC] = &cam_cc_icp_1_clk_src.clkr, + [CAM_CC_IFE_0_MAIN_CLK] = &cam_cc_ife_0_main_clk.clkr, + [CAM_CC_IFE_0_MAIN_CLK_SRC] = &cam_cc_ife_0_main_clk_src.clkr, + [CAM_CC_IFE_0_MAIN_FAST_AHB_CLK] = &cam_cc_ife_0_main_fast_ahb_clk.clkr, + [CAM_CC_IFE_0_PCP_CLK] = &cam_cc_ife_0_pcp_clk.clkr, + [CAM_CC_IFE_0_PCP_FAST_AHB_CLK] = &cam_cc_ife_0_pcp_fast_ahb_clk.clkr, + [CAM_CC_IFE_0_SCALAR_CLK] = &cam_cc_ife_0_scalar_clk.clkr, + [CAM_CC_IFE_0_SCALAR_FAST_AHB_CLK] = &cam_cc_ife_0_scalar_fast_ahb_clk.clkr, + [CAM_CC_IFE_0_TMC_CLK] = &cam_cc_ife_0_tmc_clk.clkr, + [CAM_CC_IFE_0_TMC_FAST_AHB_CLK] = &cam_cc_ife_0_tmc_fast_ahb_clk.clkr, + [CAM_CC_IFE_1_MAIN_CLK] = &cam_cc_ife_1_main_clk.clkr, + [CAM_CC_IFE_1_MAIN_CLK_SRC] = &cam_cc_ife_1_main_clk_src.clkr, + [CAM_CC_IFE_1_MAIN_FAST_AHB_CLK] = &cam_cc_ife_1_main_fast_ahb_clk.clkr, + [CAM_CC_IFE_1_PCP_CLK] = &cam_cc_ife_1_pcp_clk.clkr, + [CAM_CC_IFE_1_PCP_FAST_AHB_CLK] = &cam_cc_ife_1_pcp_fast_ahb_clk.clkr, + [CAM_CC_IFE_1_SCALAR_CLK] = &cam_cc_ife_1_scalar_clk.clkr, + [CAM_CC_IFE_1_SCALAR_FAST_AHB_CLK] = &cam_cc_ife_1_scalar_fast_ahb_clk.clkr, + [CAM_CC_IFE_1_TMC_CLK] = &cam_cc_ife_1_tmc_clk.clkr, + [CAM_CC_IFE_1_TMC_FAST_AHB_CLK] = &cam_cc_ife_1_tmc_fast_ahb_clk.clkr, + [CAM_CC_IFE_2_MAIN_CLK] = &cam_cc_ife_2_main_clk.clkr, + [CAM_CC_IFE_2_MAIN_CLK_SRC] = &cam_cc_ife_2_main_clk_src.clkr, + [CAM_CC_IFE_2_MAIN_FAST_AHB_CLK] = &cam_cc_ife_2_main_fast_ahb_clk.clkr, + [CAM_CC_IFE_2_PCP_CLK] = &cam_cc_ife_2_pcp_clk.clkr, + [CAM_CC_IFE_2_PCP_FAST_AHB_CLK] = &cam_cc_ife_2_pcp_fast_ahb_clk.clkr, + [CAM_CC_IFE_2_SCALAR_CLK] = &cam_cc_ife_2_scalar_clk.clkr, + [CAM_CC_IFE_2_SCALAR_FAST_AHB_CLK] = &cam_cc_ife_2_scalar_fast_ahb_clk.clkr, + [CAM_CC_IFE_2_TMC_CLK] = &cam_cc_ife_2_tmc_clk.clkr, + [CAM_CC_IFE_2_TMC_FAST_AHB_CLK] = &cam_cc_ife_2_tmc_fast_ahb_clk.clkr, + [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, + [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, + [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, + [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, + [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, + [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, + [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, + [CAM_CC_IPE_0_FAST_AHB_CLK] = &cam_cc_ipe_0_fast_ahb_clk.clkr, + [CAM_CC_IPE_1_AHB_CLK] = &cam_cc_ipe_1_ahb_clk.clkr, + [CAM_CC_IPE_1_CLK] = &cam_cc_ipe_1_clk.clkr, + [CAM_CC_IPE_1_CLK_SRC] = &cam_cc_ipe_1_clk_src.clkr, + [CAM_CC_IPE_1_FAST_AHB_CLK] = &cam_cc_ipe_1_fast_ahb_clk.clkr, + [CAM_CC_PLL0] = &cam_cc_pll0.clkr, + [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, + [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, + [CAM_CC_PLL2] = &cam_cc_pll2.clkr, + [CAM_CC_PLL2_OUT_EVEN] = &cam_cc_pll2_out_even.clkr, + [CAM_CC_PLL3] = &cam_cc_pll3.clkr, + [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, + [CAM_CC_PLL4] = &cam_cc_pll4.clkr, + [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, + [CAM_CC_PLL5] = &cam_cc_pll5.clkr, + [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, + [CAM_CC_PLL6] = &cam_cc_pll6.clkr, + [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, + [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, + [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, + [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, + [CAM_CC_QUP_AHBM_CLK] = &cam_cc_qup_ahbm_clk.clkr, + [CAM_CC_QUP_AHBM_CLK_SRC] = &cam_cc_qup_ahbm_clk_src.clkr, + [CAM_CC_QUP_CORE_2X_CLK] = &cam_cc_qup_core_2x_clk.clkr, + [CAM_CC_QUP_CORE_2X_CLK_SRC] = &cam_cc_qup_core_2x_clk_src.clkr, + [CAM_CC_QUP_CORE_2X_DIV_CLK_SRC] = &cam_cc_qup_core_2x_div_clk_src.clkr, + [CAM_CC_QUP_CORE_CLK] = &cam_cc_qup_core_clk.clkr, + [CAM_CC_QUP_SE_CLK] = &cam_cc_qup_se_clk.clkr, + [CAM_CC_QUP_SE_CLK_SRC] = &cam_cc_qup_se_clk_src.clkr, + [CAM_CC_SFE_LITE_0_CLK] = &cam_cc_sfe_lite_0_clk.clkr, + [CAM_CC_SFE_LITE_0_FAST_AHB_CLK] = &cam_cc_sfe_lite_0_fast_ahb_clk.clkr, + [CAM_CC_SFE_LITE_1_CLK] = &cam_cc_sfe_lite_1_clk.clkr, + [CAM_CC_SFE_LITE_1_FAST_AHB_CLK] = &cam_cc_sfe_lite_1_fast_ahb_clk.clkr, + [CAM_CC_SFE_LITE_2_CLK] = &cam_cc_sfe_lite_2_clk.clkr, + [CAM_CC_SFE_LITE_2_FAST_AHB_CLK] = &cam_cc_sfe_lite_2_fast_ahb_clk.clkr, + [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, + [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, + [CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr, + [CAM_CC_TOP_AHB_CLK] = &cam_cc_top_ahb_clk.clkr, + [CAM_CC_TOP_FAST_AHB_CLK] = &cam_cc_top_fast_ahb_clk.clkr, + [CAM_CC_TOP_IFE_0_CLK] = &cam_cc_top_ife_0_clk.clkr, + [CAM_CC_TOP_IFE_1_CLK] = &cam_cc_top_ife_1_clk.clkr, + [CAM_CC_TOP_IFE_2_CLK] = &cam_cc_top_ife_2_clk.clkr, + [CAM_CC_TOP_IFE_LITE_CLK] = &cam_cc_top_ife_lite_clk.clkr, + [CAM_CC_TOP_IPE_0_CLK] = &cam_cc_top_ipe_0_clk.clkr, + [CAM_CC_TOP_IPE_1_CLK] = &cam_cc_top_ipe_1_clk.clkr, + [CAM_CC_TOP_QUP_AHBM_CLK] = &cam_cc_top_qup_ahbm_clk.clkr, + [CAM_CC_TOP_SFE_LITE_0_CLK] = &cam_cc_top_sfe_lite_0_clk.clkr, + [CAM_CC_TOP_SFE_LITE_1_CLK] = &cam_cc_top_sfe_lite_1_clk.clkr, + [CAM_CC_TOP_SFE_LITE_2_CLK] = &cam_cc_top_sfe_lite_2_clk.clkr, + [CAM_CC_TPG_CSIPHY_RX_CLK] = &cam_cc_tpg_csiphy_rx_clk.clkr, + [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, +}; + +static struct gdsc *cam_cc_nord_gdscs[] = { + [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, + [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc, + [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc, + [CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc, + [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, + [CAM_CC_IPE_1_GDSC] = &cam_cc_ipe_1_gdsc, +}; + +static const struct qcom_reset_map cam_cc_nord_resets[] = { + [CAM_CC_CCU_BCR] = { 0x13298 }, + [CAM_CC_ICP_0_BCR] = { 0x130a0 }, + [CAM_CC_ICP_1_BCR] = { 0x130d8 }, + [CAM_CC_IFE_0_BCR] = { 0x12000 }, + [CAM_CC_IFE_1_BCR] = { 0x120c4 }, + [CAM_CC_IFE_2_BCR] = { 0x12170 }, + [CAM_CC_IPE_0_BCR] = { 0x11000 }, + [CAM_CC_IPE_1_BCR] = { 0x1105c }, + [CAM_CC_QDSS_DEBUG_BCR] = { 0x1332c }, + [CAM_CC_SFE_LITE_0_BCR] = { 0x13058 }, + [CAM_CC_SFE_LITE_1_BCR] = { 0x13070 }, + [CAM_CC_SFE_LITE_2_BCR] = { 0x13088 }, +}; + +static struct clk_alpha_pll *cam_cc_nord_plls[] = { + &cam_cc_pll0, + &cam_cc_pll2, + &cam_cc_pll3, + &cam_cc_pll4, + &cam_cc_pll5, + &cam_cc_pll6, +}; + +static const u32 cam_cc_nord_critical_cbcrs[] = { + 0x13294, /* CAM_CC_CAMNOC_XO_CLK */ + 0x13364, /* CAM_CC_CORE_AHB_CLK */ + 0x13380, /* CAM_CC_GDSC_CLK */ + 0x132e4, /* CAM_CC_QUP_SLEEP_CLK */ + 0x1339c, /* CAM_CC_SLEEP_CLK */ +}; + +static const struct regmap_config cam_cc_nord_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x17000, + .fast_io = true, +}; + +static const struct qcom_cc_driver_data cam_cc_nord_driver_data = { + .alpha_plls = cam_cc_nord_plls, + .num_alpha_plls = ARRAY_SIZE(cam_cc_nord_plls), + .clk_cbcrs = cam_cc_nord_critical_cbcrs, + .num_clk_cbcrs = ARRAY_SIZE(cam_cc_nord_critical_cbcrs), +}; + +static const struct qcom_cc_desc cam_cc_nord_desc = { + .config = &cam_cc_nord_regmap_config, + .clks = cam_cc_nord_clocks, + .num_clks = ARRAY_SIZE(cam_cc_nord_clocks), + .resets = cam_cc_nord_resets, + .num_resets = ARRAY_SIZE(cam_cc_nord_resets), + .gdscs = cam_cc_nord_gdscs, + .num_gdscs = ARRAY_SIZE(cam_cc_nord_gdscs), + .use_rpm = true, + .driver_data = &cam_cc_nord_driver_data, +}; + +static const struct of_device_id cam_cc_nord_match_table[] = { + { .compatible = "qcom,nord-camcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, cam_cc_nord_match_table); + +static int cam_cc_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &cam_cc_nord_desc); +} + +static struct platform_driver cam_cc_nord_driver = { + .probe = cam_cc_nord_probe, + .driver = { + .name = "camcc-nord", + .of_match_table = cam_cc_nord_match_table, + }, +}; + +module_platform_driver(cam_cc_nord_driver); + +MODULE_DESCRIPTION("QTI CAMCC Nord Driver"); +MODULE_LICENSE("GPL"); From 71ffdd20e14b8bc33b7d870b41ce41d91b5211a3 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 6 Aug 2026 16:23:13 +0530 Subject: [PATCH 11/11] arm64: dts: qcom: nord-embedded: update the videocc header for video clocks Nord is reusing the Glymur videocc and thus include the correct header for the clocks to be referenced by consumers. Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi index 0187d85bdd8d4..74a069eced695 100644 --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi @@ -3,6 +3,7 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include #include #include #include @@ -11,7 +12,6 @@ #include #include #include -#include #include #include #include