From fb5db73844bcc9920b030afb0133da4373728bca Mon Sep 17 00:00:00 2001 From: Anurag Pateriya Date: Thu, 6 Aug 2026 13:50:03 +0530 Subject: [PATCH 1/3] FROMLIST: dt-bindings: remoteproc: qcom,nord-pas: Document Nord PAS Add a dedicated binding for the Qualcomm Nord SoC PAS devices: ADSP and CDSPs. Nord ADSP uses CX and MX power domains while the CDSPs add an NSP domain on top of that. Nord ADSP was previously documented in qcom,sm8550-pas.yaml, which hardcodes a two-entry power-domains list and therefore cannot express the third NSP domain the CDSPs require. Drop the Nord bits from that binding so Nord is described in exactly one place. This supersedes commit a6021174e275 ("FROMLIST: dt-bindings: remoteproc: qcom,sm8550-pas: Document Nord ADSP"). Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260729023508.879752-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo Signed-off-by: Anurag Pateriya --- .../bindings/remoteproc/qcom,nord-pas.yaml | 173 ++++++++++++++++++ .../bindings/remoteproc/qcom,sm8550-pas.yaml | 19 -- 2 files changed, 173 insertions(+), 19 deletions(-) create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,nord-pas.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,nord-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,nord-pas.yaml new file mode 100644 index 0000000000000..e90d2953ba692 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,nord-pas.yaml @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,nord-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Nord SoC Peripheral Authentication Service + +maintainers: + - Shawn Guo + +description: + Qualcomm Nord SoC Peripheral Authentication Service loads and boots firmware + on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,nord-adsp-pas + - qcom,nord-cdsp0-pas + - qcom,nord-cdsp1-pas + - qcom,nord-cdsp2-pas + - qcom,nord-cdsp3-pas + + power-domains: + minItems: 2 + items: + - description: CX power domain + - description: MX power domain + - description: NSP power domain + + power-domain-names: + minItems: 2 + items: + - const: cx + - const: mx + - const: nsp + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + firmware-name: + items: + - description: Firmware name of the Hexagon core + - description: Firmware name of the Hexagon Devicetree + + memory-region: + items: + - description: Memory region for main Firmware authentication + - description: Memory region for Devicetree Firmware authentication + + interrupts: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + +required: + - compatible + - reg + - memory-region + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,nord-adsp-pas + then: + properties: + power-domains: + maxItems: 2 + power-domain-names: + maxItems: 2 + else: + properties: + power-domains: + minItems: 3 + power-domain-names: + minItems: 3 + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #define IPCC_MPROC_ADSP0 + + remoteproc@4c00000 { + compatible = "qcom,nord-adsp-pas"; + reg = <0x04c00000 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interrupts-extended = <&intc GIC_SPI 159 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + memory-region = <&hpass_dsp0_mem>, <&hpass_dsp0_dtb_mem>; + + firmware-name = "qcom/nord/adsp.mbn", + "qcom/nord/adsp_dtb.mbn"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names = "cx", + "mx"; + + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_ADSP0 + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_ADSP0 IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "adsp"; + qcom,remote-pid = <2>; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index f9385d8e6a8a6..bd5c7c3e2f306 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -17,7 +17,6 @@ properties: compatible: oneOf: - enum: - - qcom,nord-adsp-pas - qcom,sdx75-mpss-pas - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas @@ -141,7 +140,6 @@ allOf: - qcom,kaanapali-cdsp-pas - qcom,maili-adsp-pas - qcom,maili-cdsp-pas - - qcom,nord-adsp-pas - qcom,sm8750-adsp-pas then: properties: @@ -246,23 +244,6 @@ allOf: - const: lcx - const: lmx - - if: - properties: - compatible: - contains: - enum: - - qcom,nord-adsp-pas - then: - properties: - power-domains: - items: - - description: CX power domain - - description: MX power domain - power-domain-names: - items: - - const: cx - - const: mx - - if: properties: compatible: From 45e2321514888c69d3ea5f72e435ba759ce7693b Mon Sep 17 00:00:00 2001 From: Anurag Pateriya Date: Thu, 6 Aug 2026 14:04:26 +0530 Subject: [PATCH 2/3] FROMLIST: remoteproc: qcom: pas: Add Nord CDSP support Add support for the 4 CDSPs found on Nord SoC. Each CDSP uses the CX, MX and NSP power domains, and is cold booted by Linux, so no early_boot flag is needed unlike the Nord ADSP. The device tree nodes for these already exist in nord.dtsi, with the power domains and XO clock supplied from nord-embedded.dtsi, but the driver had no matching resource descriptors, so the CDSP nodes did not probe. Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260729023508.879752-4-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo Signed-off-by: Anurag Pateriya --- drivers/remoteproc/qcom_q6v5_pas.c | 88 ++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index 486362704e7fb..3a30cbd3ce2b6 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -1555,6 +1555,90 @@ static const struct qcom_pas_data nord_adsp_resource = { .smem_host_id = 2, }; +static const struct qcom_pas_data nord_cdsp0_resource = { + .crash_reason_smem = 601, + .firmware_name = "cdsp.mbn", + .dtb_firmware_name = "cdsp_dtb.mbn", + .pas_id = 18, + .dtb_pas_id = 37, + .minidump_id = 7, + .auto_boot = true, + .proxy_pd_names = (char*[]){ + "cx", + "mx", + "nsp", + NULL + }, + .load_state = "cdsp", + .ssr_name = "cdsp0", + .sysmon_name = "cdsp0", + .ssctl_id = 0x17, + .smem_host_id = 5, +}; + +static const struct qcom_pas_data nord_cdsp1_resource = { + .crash_reason_smem = 633, + .firmware_name = "cdsp1.mbn", + .dtb_firmware_name = "cdsp1_dtb.mbn", + .pas_id = 30, + .dtb_pas_id = 59, + .minidump_id = 20, + .auto_boot = true, + .proxy_pd_names = (char*[]){ + "cx", + "mx", + "nsp", + NULL + }, + .load_state = "cdsp1", + .ssr_name = "cdsp1", + .sysmon_name = "cdsp1", + .ssctl_id = 0x20, + .smem_host_id = 69, +}; + +static const struct qcom_pas_data nord_cdsp2_resource = { + .crash_reason_smem = 665, + .firmware_name = "cdsp2.mbn", + .dtb_firmware_name = "cdsp2_dtb.mbn", + .pas_id = 57, + .dtb_pas_id = 60, + .minidump_id = 29, + .auto_boot = true, + .proxy_pd_names = (char*[]){ + "cx", + "mx", + "nsp", + NULL + }, + .load_state = "cdsp2", + .ssr_name = "cdsp2", + .sysmon_name = "cdsp2", + .ssctl_id = 0x1f, + .smem_host_id = 133, +}; + +static const struct qcom_pas_data nord_cdsp3_resource = { + .crash_reason_smem = 666, + .firmware_name = "cdsp3.mbn", + .dtb_firmware_name = "cdsp3_dtb.mbn", + .pas_id = 58, + .dtb_pas_id = 61, + .minidump_id = 30, + .auto_boot = true, + .proxy_pd_names = (char*[]){ + "cx", + "mx", + "nsp", + NULL + }, + .load_state = "cdsp3", + .ssr_name = "cdsp3", + .sysmon_name = "cdsp3", + .ssctl_id = 0x1a, + .smem_host_id = 197, +}; + static const struct qcom_pas_data sm8450_mpss_resource = { .crash_reason_smem = 421, .firmware_name = "modem.mdt", @@ -1817,6 +1901,10 @@ static const struct of_device_id qcom_pas_of_match[] = { { .compatible = "qcom,milos-mpss-pas", .data = &sm8450_mpss_resource }, { .compatible = "qcom,milos-wpss-pas", .data = &sc7280_wpss_resource }, { .compatible = "qcom,nord-adsp-pas", .data = &nord_adsp_resource }, + { .compatible = "qcom,nord-cdsp0-pas", .data = &nord_cdsp0_resource }, + { .compatible = "qcom,nord-cdsp1-pas", .data = &nord_cdsp1_resource }, + { .compatible = "qcom,nord-cdsp2-pas", .data = &nord_cdsp2_resource }, + { .compatible = "qcom,nord-cdsp3-pas", .data = &nord_cdsp3_resource }, { .compatible = "qcom,msm8226-adsp-pil", .data = &msm8996_adsp_resource }, { .compatible = "qcom,msm8953-adsp-pil", .data = &msm8996_adsp_resource }, { .compatible = "qcom,msm8974-adsp-pil", .data = &msm8996_adsp_resource }, From 61d0d260b7a7aaa2c0a44313ff72964cd31668a0 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Thu, 6 Aug 2026 12:26:24 +0530 Subject: [PATCH 3/3] PENDING: arm64: dts: qcom: nord: Add adreno and PCIe SMMU nodes Add the Adreno GPU SMMMUs (MMU-500) for both GPU instances and the PCIe SMMU (SMMUv3) nodes. Wire up the gpucc clock and power domain on both adreno SMMU nodes in nord-embedded.dtsi for embedded Nord variants where gpucc is available. Signed-off-by: Bibek Kumar Patro --- arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 12 +++ arch/arm64/boot/dts/qcom/nord.dtsi | 95 +++++++++++++++++++++ 2 files changed, 107 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi index ad2596806a6e2..010080e8d04fb 100644 --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi @@ -2228,3 +2228,15 @@ maximum-speed = "high-speed"; qcom,select-utmi-as-pipe-clk; }; + +&adreno_smmu_0 { + clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>; + clock-names = "hlos"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; +}; + +&adreno_smmu_1 { + clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>; + clock-names = "hlos"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; +}; diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi index 34393c63a4c0e..4849f9b283883 100644 --- a/arch/arm64/boot/dts/qcom/nord.dtsi +++ b/arch/arm64/boot/dts/qcom/nord.dtsi @@ -2323,6 +2323,101 @@ ; }; + adreno_smmu_0: iommu@3da0000 { + compatible = "qcom,nord-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-coherent; + }; + + adreno_smmu_1: iommu@98a0000 { + compatible = "qcom,nord-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x098a0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-coherent; + }; + + pcie_smmu: iommu@9980000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x09980000 0x0 0x20000>; + interrupts = , + , + ; + interrupt-names = "eventq", + "cmdq-sync", + "gerror"; + dma-coherent; + #iommu-cells = <1>; + }; + intc: interrupt-controller@17000000 { compatible = "arm,gic-v3"; reg = <0x0 0x17000000 0x0 0x10000>,