Add two extra GPIO banks to the peripherals

[rrbutani]

what

We want to support use cases that require more than 8 GPIO pins. At the same time we don't want to limit device implementations of the platform to devices that have 24+ pins available.

So, it's time to introduce optional peripherals, something we've discussed before re: other peripherals like the Disk peripheral (#54).

steps

• groundwork for optional peripherals
• add extra mem-mapped I/O entries for the two extra banks (CR and DR, bank wide, and interrupt vectors)
• extend the Control trait to support querying for the presence of optional peripherals
• extend the Control trait to have methods for the extra gpio banks (get_states, get_readings)
  • asking about extra banks is fallible since they may not exist
  • the "right way" to model this is to grow get_extra_gpio_states/get_extra_gpio_readings functions that take a GpioBank arg but... I think it's okay to just modify the existing get_gpio_states/get_gpio_readings functions and for users to Know that the first bank will always be present
• update the GPIO TRAPs to support taking pin numbers from 0 through 23
• update the GPIO TRAP docs to reflect the change above; add traps::gpio module level docs that explain how to translate from pin names to numbers (i.e. GB5 = 1 * 8 + 5 = 13, etc., show a full table too (and then link to that section of the module level docs from all the GPIO TRAP docs)
• update the GPIO TRAP tests to test these extra pins
• update the TUI to:
  • support querying for the presence of extra GPIO banks
  • support displaying the state of the pins in the extra banks, if present

where

branch: feat/extra-gpio-banks

open questions

Pin numbering? I see two options:

• bank prefixed; i.e. GA0, GA1, ..., GA7, GB0, ..., GB7, GC0, ...
  • internally we're going to just have three GPIO peripherals, each of which will take a GpioPin that's G0 through G7 so the upside to this option is that the internals match the names we're using externally
  • distinguishing the banks externally is valuable if we expose TRAPs that operate on the full banks (Add bank wide GPIO TRAPs for read/write #177)
• flat: i.e. G0, ..., G23
  • the upside to this approach is the numbers match what users will feed the GPIO TRAPs

I've picked the 1st option for now (it doesn't seem too onerous to have students figure out that GC3 -> #19, etc.) but I'm not totally sold on it.