I am an Electrical and Electronic Engineer and University of Toronto graduate building hands-on expertise in RTL design, RISC-V processor microarchitecture, ASIC synthesis, static timing analysis, verification, and physical implementation. My projects progress from modular RTL and custom CPU design through SKY130 technology mapping, multi-corner STA, place-and-route, and DRC/LVS, toward ongoing development of AtlasRV, a five-stage RV32I RISC-V processor. I am also developing modern verification capability through SystemVerilog, assertions, scoreboards, coverage, and regression, with UVM environments as a planned next step.
-
BSc Electrical & Electronic Engineering
-
M.Eng. Biomedical Engineering, University of Toronto
-
Currently working in a professional role outside the semiconductor industry while actively transitioning into ASIC/VLSI engineering
-
Building AtlasRV, an ongoing RV32I RISC-V processor project, alongside SystemVerilog verification and open-source silicon work
-
Reach me at famoustay55@gmail.com
RISC-V Processor Design AtlasRV RV32I processor architecture, single-cycle reference implementation, five-stage pipeline development (in progress), forwarding and hazard detection (planned), load-use stalls and branch/jump flush handling (planned), processor verification.
RTL and Digital Design SystemVerilog and Verilog, finite-state machines, datapath/control partitioning, memory interfaces, register files, processor and peripheral architecture.
Verification Directed and self-checking testbenches, waveform debugging, simulation regression, SystemVerilog assertions and scoreboards (in development), functional coverage and constrained-random verification (in development), planned UVM methodology.
ASIC Front-End Yosys synthesis, SKY130 technology mapping, SDC development, OpenSTA setup/hold analysis, multi-corner timing analysis, timing closure, CDC/RDC-aware constraints.
Physical Design OpenLane/OpenROAD, floorplanning, PDN, placement, CTS, routing, post-route STA, DRC, LVS, antenna verification, GDSII generation.
Open-Source Silicon AtlasRV RISC-V processor development, Ibex (lowRISC) forked for study with contribution work planned, OpenROAD/OpenLane ecosystem, future Tiny Tapeout or MPW participation as a long-term goal.
Stage Area Status 1 RTL Foundations - combinational/sequential logic, FSMs, parameterized modules Completed 2 RTL Simulation and Directed Verification - self-checking testbenches, waveform debugging, regression Completed 3 ASIC Synthesis and Automation - Yosys, TCL/Python scripting, SKY130 technology mapping Completed 4 Static Timing Analysis - SDC, setup/hold analysis, multi-corner OpenSTA, timing closure Completed 5 Physical Design - OpenLane/OpenROAD, floorplan, PDN, placement, CTS, routing, DRC/LVS, GDSII Completed 6 AtlasRV RISC-V Processor - RV32I single-cycle reference and five-stage pipeline development Active 7 SystemVerilog Verification - interfaces, assertions, scoreboards, randomized testing, coverage Active 8 UVM Verification - agents, sequences, drivers, monitors, scoreboards, coverage-driven verification Planned 9 Open-Source Contribution - Ibex, OpenROAD, OpenTitan, or related hardware projects Planned 10 Formal Verification - SVA, SymbiYosys, bounded proofs, protocol/property checking Planned 11 DFT and Low-Power Design - scan, ATPG concepts, clock gating, UPF foundations Planned 12 Advanced ASIC Implementation - larger-core synthesis, STA, GLS, and physical design Planned 13 Tapeout / Open-Source Silicon - Tiny Tapeout, MPW, or equivalent shuttle Goal Status: Ongoing
Ongoing SystemVerilog RISC-V RV32I processor project targeting a five-stage in-order pipeline, hazard handling, forwarding, verification, and future ASIC implementation. Implemented: RV32I package/control definitions, ALU, register file, immediate generator, decoder, branch unit, load/store unit, an in-progress single-cycle reference core, and directed SystemVerilog testbenches for each module. Planned: pipeline registers, forwarding, load-use hazard detection, stalls, branch/jump flushes, assertions, coverage, UVM, synthesis, STA, and physical design.
SPI-configurable UART controller with UART TX/RX, CRC-8, watchdog supervision, sticky fault handling, safe-state control, interrupt generation, CDC-aware synchronizers, and self-checking Verilog verification at both block and integrated system level.
SKY130 HD technology mapping (843 cells, 10,242.32 sq um), multi-corner OpenSTA (TT/SS/FF) with closed 100 MHz pre-layout timing, SDC development, timing-path optimization, and CDC/RDC-aware review. Pre-layout implementation readiness; physical design (floorplan-to-GDSII) is a separate future stage.
Complete RTL/netlist-to-GDSII backend implementation using OpenLane/OpenROAD: floorplanning, PDN, placement, CTS, routing, post-route STA, DRC, LVS, antenna checks, and final GDSII generation, with clean signoff across all checks.
Yosys synthesis and SKY130 HD technology mapping of the 8-bit CPU (761 cells, 8301.7 sq um), OpenSTA timing analysis, and 100 MHz timing closure with critical-path investigation.
Custom 8-bit single-cycle CPU with a custom instruction set, modular datapath and control (program counter, decoder, control unit, register file, ALU, data memory, branch unit), verified with directed testbenches and waveform inspection.
Compact foundational projects, still public but not primary portfolio pieces:
- Parameterized Modular ALU - arithmetic, logic, comparison, and shift units with ModelSim verification
- 16-Bit Register Design - parameterized 8x16 register file with read/write control and testbench verification
- Linear Feedback Shift Register (LFSR) Design - 8-bit LFSR for pseudo-random sequence generation
RTL and Processor Design: SystemVerilog, Verilog, RISC-V, RV32I, Icarus Verilog, ModelSim, GTKWave
Verification: directed and self-checking testbenches, regression, waveform debugging, SVA development (in progress), coverage development (in progress), UVM (planned)
ASIC Front-End: Yosys, OpenSTA, SDC, TCL, Python, SKY130
Physical Design and Signoff: OpenLane, OpenROAD, Magic, KLayout, Netgen, GDSII, DRC, LVS
Analog IC Design: Cadence Virtuoso, Spectre, ADE, ViVA