Harinandanan Ajith Maya — Portfolio

Hardware engineer portfolio website: FPGA · RTL Design · SoC Integration · RISC-V

Tech Stack

• Next.js 14 (static export)
• Tailwind CSS v3
• Google Fonts: Space Grotesk, Inter, JetBrains Mono

Quick Start

npm install
npm run dev       # http://localhost:3000
npm run build     # production build + static export → /out

Deployment

After npm run build, the /out folder is a fully static site. Deploy to: Vercel, Netlify, GitHub Pages, or any static host.

Vercel (recommended)

npx vercel --prod

GitHub Pages

Push /out to gh-pages branch, or configure GitHub Actions.

Customisation

Update contact / links

Edit pages/index.jsx:

• Email: search harinandanan.am@gmail.com
• LinkedIn: search linkedin.com/in/harinandanan-am
• GitHub: search github.com/harinandanan-am

Add real resume PDF files

Place PDFs in /public/:

• public/resume_fpga.pdf
• public/resume_rtl.pdf
• public/resume_soc_riscv.pdf

Then change the resume button hrefs from mailto: to /resume_fpga.pdf etc.

Colors

All colours are in tailwind.config.js under theme.extend.colors.

Structure

├── components/
│   ├── Nav.jsx              Navigation bar
│   └── TimingDiagram.jsx    SVG timing diagram decorations
├── pages/
│   ├── _app.jsx
│   ├── _document.jsx
│   └── index.jsx            All page sections
├── styles/
│   └── globals.css
├── tailwind.config.js
├── next.config.js
└── package.json

SEO

Meta tags are in pages/_document.jsx. Update og:url with your deployed domain.

Resume Variants

Three targeted resumes were produced alongside this site:

• resume_fpga — FPGA design, prototyping, emulation, hardware bring-up
• resume_rtl — RTL design, verification, ASIC flow, synthesis
• resume_soc_riscv — SoC integration, RISC-V, multicore, IP integration