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Prototype NVFP4 with FP8 UE5M3 block scales - #3325

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timmoon10:nvfp4-ue5m3-prototype
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Prototype NVFP4 with FP8 UE5M3 block scales#3325
timmoon10 wants to merge 14 commits into
NVIDIA:mainfrom
timmoon10:nvfp4-ue5m3-prototype

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Description

This is a proof-of-concept for NVFP4 with FP8 UE5M3 block scales. Quantization is supported, but GEMMs are not yet available.

Type of change

  • Documentation change (change only to the documentation, either a fix or a new content)
  • Bug fix (non-breaking change which fixes an issue)
  • New feature (non-breaking change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to not work as expected)
  • Infra/Build change
  • Code refactoring

Changes

  • Support NVFP4 tensors with UE5M3 scales
  • Support UE5M3 scales in NVFP4 quantize/dequantize kernels
  • Support UE5M3 scales in NVFP4 quantizers

Checklist:

  • I have read and followed the contributing guidelines
  • The functionality is complete
  • I have commented my code, particularly in hard-to-understand areas
  • I have made corresponding changes to the documentation
  • My changes generate no new warnings
  • I have added tests that prove my fix is effective or that my feature works
  • New and existing unit tests pass locally with my changes

Co-authored-by: Teddy Do <tdophung@nvidia.com>
Co-authored-by: Varun Thumbe <vthumbe@nvidia.com>
Signed-off-by: Tim Moon <tmoon@nvidia.com>
@timmoon10 timmoon10 added the enhancement New feature or request label Aug 7, 2026
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/te-ci L1

* [PyTorch] Enable e5m3 fused GEMM kernels from cuDNN

Signed-off-by: Kaining Zhong <kainingz@nvidia.com>

* have to pad to 256 to use cuDNN

Signed-off-by: Kaining Zhong <kainingz@nvidia.com>

* fix: need to pass scale_dtype

Signed-off-by: Kaining Zhong <kainingz@nvidia.com>

* route wgrad to cuDNN's wgrad API

Signed-off-by: Kaining Zhong <kainingz@nvidia.com>

* Support grouped linear with NVFP4-UE5M3

NVFP4-UE5M3 grouped GEMM falls back to dense GEMMs. Generalize usage of wgrad kernel and use when tensors sizes are not 256-aligned. Fix inconsistent m,n,k GEMM notation. Remove ue5m3 hacks in op fuser tests. Add ue5m3 to grouped MLP tests.

Signed-off-by: Tim Moon <tmoon@nvidia.com>

* Fix typos

Co-authored-by: Codex <noreply@openai.com>
Signed-off-by: Tim Moon <tmoon@nvidia.com>

---------

Signed-off-by: Kaining Zhong <kainingz@nvidia.com>
Signed-off-by: Tim Moon <tmoon@nvidia.com>
Co-authored-by: Tim Moon <tmoon@nvidia.com>
Co-authored-by: Codex <noreply@openai.com>
bias = bias.contiguous().as_strided((M, 1), (1, M))

# Prepare for output
out = validate_or_alloc_output(out, out_shape, out_dtype, device)

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You can remove this line now since you've done this at line 530 just before "Trivial cases"

Comment on lines 16 to 21
#ifdef __cplusplus
#define NVTE_NVFP4_SCALE_DTYPE_DEFAULT = kNVTEFloat8E4M3
extern "C" {
#else
#define NVTE_NVFP4_SCALE_DTYPE_DEFAULT
#endif

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Won't this break ABI compatibility if accessing as C functions? It's also quite hacky and nonstandard.

We should check, but I believe these are advanced functions that are only used for our Mcore DDP integration. If this is true, I think it's fine to break backward compatibility and just add the scale dtype as a normal function arg.

@tdophung tdophung Aug 14, 2026

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yesh it does break ABI. Since I did not want to create separate function for each (like a _v2) with the extra scale_dtype arg, I resorted to this thinking that it is a nvfp4-plus-devel branch specifically anyways so it should be ok to assume that people that intentionally uses it (Mcore) would always pass in the scale_dtype.

But i think you are right, that it is hacky/deceiving, so I'll just make it a normal arg

Signed-off-by: Tim Moon <tmoon@nvidia.com>
Signed-off-by: Tim Moon <tmoon@nvidia.com>
@timmoon10
timmoon10 force-pushed the nvfp4-ue5m3-prototype branch from 0987860 to ab3a9b3 Compare August 14, 2026 12:09
Comment on lines +589 to +591
# cuDNN's grouped quant kernel requires M to be divisible by 256 so we need to pad it
N_padded = ceil_div(N, 256) * 256
if N_padded != N:

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All of this padding logic is unnecessary since unaligned data goes to the wgrad kernel.

timmoon10 and others added 5 commits August 14, 2026 12:44
@timmoon10
timmoon10 marked this pull request as ready for review August 17, 2026 21:35
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greptile-apps Bot commented Aug 17, 2026

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Greptile Summary

The PR prototypes NVFP4 quantization with UE5M3 block scales across the CUDA core and PyTorch frontend.

  • Adds UE5M3 scale dtype propagation through NVFP4 tensor storage, quantizers, cast/dequantize kernels, and bindings.
  • Updates grouped-linear and fused grouped-MLP handling for the new scale format.
  • Adds C++ and PyTorch coverage for quantization, dequantization, grouped operations, and exact scale behavior.

Confidence Score: 4/5

The PR is not yet safe to merge because single-group NVFP4 grouped-MLP execution still fails while reconstructing a dense NVFP4 tensor.

The single-group grouped-MLP helper omits the required scale_dtype keyword when constructing NVFP4Tensor, so reachable forward and backward paths raise TypeError before GEMM or scale swizzling.

Files Needing Attention: transformer_engine/pytorch/ops/fused/grouped_mlp.py

Important Files Changed

Filename Overview
transformer_engine/common/cast/nvfp4/core_nvfp4.cuh Generalizes NVFP4 scale handling so quantization kernels can operate with E4M3 or UE5M3 scales.
transformer_engine/pytorch/tensor/nvfp4_tensor.py Propagates the scale dtype through Python NVFP4 tensor metadata and construction.
transformer_engine/pytorch/csrc/quantizer.cpp Extends the native quantizer bridge to carry UE5M3 NVFP4 scale metadata.
transformer_engine/pytorch/ops/fused/grouped_mlp.py Extends fused grouped-MLP quantization and cuDNN operand handling for UE5M3 scales.
tests/pytorch/nvfp4/test_nvfp4_quantize_exact.py Adds exact-reference coverage for NVFP4 quantization using the new scale format.

Flowchart

%%{init: {'theme': 'neutral'}}%%
flowchart LR
  Recipe["NVFP4 recipe<br/>E4M3 or UE5M3 scales"] --> Quantizer["PyTorch NVFP4Quantizer"]
  Quantizer --> Binding["PyTorch C++ binding"]
  Binding --> Core["NVFP4 CUDA quantize/dequantize kernels"]
  Core --> Storage["FP4 data + typed FP8 block scales"]
  Storage --> Tensor["NVFP4Tensor / GroupedTensor"]
  Tensor --> Ops["Grouped-linear and grouped-MLP paths"]
Loading

Reviews (2): Last reviewed commit: "Fix compile error" | Re-trigger Greptile

Comment on lines 880 to 882
if not fused_op_cls.is_supported():
assert False ### TODO Remove
return ops

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P1 Unsupported fusion aborts fallback

When the optional fused grouped-MLP implementation is unavailable, this assertion aborts pipeline construction instead of returning the original operations, breaking grouped MLP execution on unsupported architectures, disabled feature configurations, or installations without the required kernels.

Suggested change
if not fused_op_cls.is_supported():
assert False ### TODO Remove
return ops
if not fused_op_cls.is_supported():
return ops

Knowledge Base Used: PyTorch Fusible-Operation Framework

Signed-off-by: Tim Moon <tmoon@nvidia.com>
@timmoon10

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/te-ci L1

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4 participants