Prototype NVFP4 with FP8 UE5M3 block scales - #3325
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Co-authored-by: Teddy Do <tdophung@nvidia.com> Co-authored-by: Varun Thumbe <vthumbe@nvidia.com> Signed-off-by: Tim Moon <tmoon@nvidia.com>
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* [PyTorch] Enable e5m3 fused GEMM kernels from cuDNN Signed-off-by: Kaining Zhong <kainingz@nvidia.com> * have to pad to 256 to use cuDNN Signed-off-by: Kaining Zhong <kainingz@nvidia.com> * fix: need to pass scale_dtype Signed-off-by: Kaining Zhong <kainingz@nvidia.com> * route wgrad to cuDNN's wgrad API Signed-off-by: Kaining Zhong <kainingz@nvidia.com> * Support grouped linear with NVFP4-UE5M3 NVFP4-UE5M3 grouped GEMM falls back to dense GEMMs. Generalize usage of wgrad kernel and use when tensors sizes are not 256-aligned. Fix inconsistent m,n,k GEMM notation. Remove ue5m3 hacks in op fuser tests. Add ue5m3 to grouped MLP tests. Signed-off-by: Tim Moon <tmoon@nvidia.com> * Fix typos Co-authored-by: Codex <noreply@openai.com> Signed-off-by: Tim Moon <tmoon@nvidia.com> --------- Signed-off-by: Kaining Zhong <kainingz@nvidia.com> Signed-off-by: Tim Moon <tmoon@nvidia.com> Co-authored-by: Tim Moon <tmoon@nvidia.com> Co-authored-by: Codex <noreply@openai.com>
| bias = bias.contiguous().as_strided((M, 1), (1, M)) | ||
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| # Prepare for output | ||
| out = validate_or_alloc_output(out, out_shape, out_dtype, device) |
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You can remove this line now since you've done this at line 530 just before "Trivial cases"
| #ifdef __cplusplus | ||
| #define NVTE_NVFP4_SCALE_DTYPE_DEFAULT = kNVTEFloat8E4M3 | ||
| extern "C" { | ||
| #else | ||
| #define NVTE_NVFP4_SCALE_DTYPE_DEFAULT | ||
| #endif |
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Won't this break ABI compatibility if accessing as C functions? It's also quite hacky and nonstandard.
We should check, but I believe these are advanced functions that are only used for our Mcore DDP integration. If this is true, I think it's fine to break backward compatibility and just add the scale dtype as a normal function arg.
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yesh it does break ABI. Since I did not want to create separate function for each (like a _v2) with the extra scale_dtype arg, I resorted to this thinking that it is a nvfp4-plus-devel branch specifically anyways so it should be ok to assume that people that intentionally uses it (Mcore) would always pass in the scale_dtype.
But i think you are right, that it is hacky/deceiving, so I'll just make it a normal arg
Signed-off-by: Tim Moon <tmoon@nvidia.com>
Signed-off-by: Tim Moon <tmoon@nvidia.com>
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| # cuDNN's grouped quant kernel requires M to be divisible by 256 so we need to pad it | ||
| N_padded = ceil_div(N, 256) * 256 | ||
| if N_padded != N: |
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All of this padding logic is unnecessary since unaligned data goes to the wgrad kernel.
Signed-off-by: Tim Moon <tmoon@nvidia.com>
for more information, see https://pre-commit.ci
Signed-off-by: Tim Moon <tmoon@nvidia.com>
for more information, see https://pre-commit.ci
Signed-off-by: Tim Moon <tmoon@nvidia.com>
Greptile SummaryThe PR prototypes NVFP4 quantization with UE5M3 block scales across the CUDA core and PyTorch frontend.
Confidence Score: 4/5The PR is not yet safe to merge because single-group NVFP4 grouped-MLP execution still fails while reconstructing a dense NVFP4 tensor. The single-group grouped-MLP helper omits the required Files Needing Attention: transformer_engine/pytorch/ops/fused/grouped_mlp.py Important Files Changed
Flowchart%%{init: {'theme': 'neutral'}}%%
flowchart LR
Recipe["NVFP4 recipe<br/>E4M3 or UE5M3 scales"] --> Quantizer["PyTorch NVFP4Quantizer"]
Quantizer --> Binding["PyTorch C++ binding"]
Binding --> Core["NVFP4 CUDA quantize/dequantize kernels"]
Core --> Storage["FP4 data + typed FP8 block scales"]
Storage --> Tensor["NVFP4Tensor / GroupedTensor"]
Tensor --> Ops["Grouped-linear and grouped-MLP paths"]
Reviews (2): Last reviewed commit: "Fix compile error" | Re-trigger Greptile |
| if not fused_op_cls.is_supported(): | ||
| assert False ### TODO Remove | ||
| return ops |
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Unsupported fusion aborts fallback
When the optional fused grouped-MLP implementation is unavailable, this assertion aborts pipeline construction instead of returning the original operations, breaking grouped MLP execution on unsupported architectures, disabled feature configurations, or installations without the required kernels.
| if not fused_op_cls.is_supported(): | |
| assert False ### TODO Remove | |
| return ops | |
| if not fused_op_cls.is_supported(): | |
| return ops |
Knowledge Base Used: PyTorch Fusible-Operation Framework
Signed-off-by: Tim Moon <tmoon@nvidia.com>
for more information, see https://pre-commit.ci
Signed-off-by: Tim Moon <tmoon@nvidia.com>
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/te-ci L1 |
Description
This is a proof-of-concept for NVFP4 with FP8 UE5M3 block scales. Quantization is supported, but GEMMs are not yet available.
Type of change
Changes
Checklist: