Startup time: 8812AU rows + true-VBUS-cold harness (REGRESS_VBUS_MAP)#210
Merged
Conversation
Fills the missing RTL8812AU rows in docs/startup-time.md — devourer 1.7 s vs 88XXau 2.1 s from true cold (median of 4, 100% pass), 1.7/2.0 s warm — measured on a healthy unit after root-causing issue #205 to a dying adapter (stochastic garbage EFUSE reads + 8051 never booting FW), not a port and not a driver cold-init gap. Harness additions the measurement needed, kept for reuse: - tests/regress.py: REGRESS_VBUS_MAP="<sysfs_id>=<hubloc>:<port>" makes usb_port_power_cycle cut real VBUS via uhubctl (per-cell first-plug cold) instead of the authorized-toggle, for DUTs on switchable hub ports. Never map root ports. - tests/cold_first_init_8812au.sh: per-rep true-cold first-init discriminator (unit vs port vs driver), flood-verified hearing, temp-blacklists the in-tree rtw88 module so nothing touches the chip before the driver under test. - tests/bench_8812au_row.sh: the row measurement (two same-PID units on the rig; powers the spare off, blacklists rtw88_8812au, runs bench_init with the VBUS map). - docs/startup-time.md: a third harness-honesty trap — in-tree rtw88 auto-probes at every enumeration (udev modalias survives modprobe -r) and firmware-downloads into the chip before any timed window; temp blacklist required. Plus an authorized-toggle caveat: 1 in 8 toggled-warm 8812AU inits came up RX-deaf with a green init (0 in 8 VBUS-cold). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Closes #205.
Investigation verdict (issue #205's three candidates)
Ran a per-rep true-cold discriminator on two identical 8812AU units (the suspect + a fresh one), both on uhubctl-switchable hub ports, with a verified-radiating 8814AU beacon flood as the hearing reference and the in-tree
rtw88_8812autemp-blacklisted so nothing touches the chip before the driver under test:power_on3–6 ms;hal_init~950 ms)EEPROM ID=0x7114/0xeeee/0x0031/0x1000/0x1029/0x8100… vs true0x8129, different every read) →rfe_type=0, PA/LNA zeroed → wrong PHY tables → deaf with a green init. Independently, the 8051 never boots firmware (polling_fwdl_chksumreport never asserts) — the same pathology behind the in-tree rtw88 driver's perpetual probe failure on this unit (0/10+ ever, vs the new unit's first-try pass; that probe result is a 5-second smoke test for this failure mode). A warm re-read recovers the ID but the map tail stays erased-looking (ThermalMeter 0xFF, RFE 0) — so an EFUSE-read-retry in the library would not save such a unit; not added.power_on, ~950 mshal_init, hears instantly. The issue's "suspicious 20 ms power_on" was normal behaviour. TheInitLLTTable8812Aaborts did not reproduce in 11 inits (clean or contaminated) — the dying unit's failure locus is stochastic and that was its worst (boot-cold) phase.Methodology confound found along the way: every historical "first init from true cold" data point was contaminated — modern kernels ship in-tree rtw88 USB drivers for all supported chips, udev auto-loads them by modalias at every enumeration (a bare
modprobe -rdoesn't survive re-enumeration), and their probe firmware-downloads into the chip before devourer or the vendor.koever opens it. On the dying unit that probe also fails, leaving the chip half-wedged mid-fwdl. Neither driver had ever seen pristine cold on this rig.What this PR adds
docs/startup-time.md— the missing RTL8812AU rows, measured on the healthy unit:authorized-toggle caveat: 1 of 8 toggled-warm inits came up RX-deaf with a fully green init (0 of 8 VBUS-cold) — suspect the toggle before the driver or the unit.tests/regress.py—REGRESS_VBUS_MAP="<sysfs_id>=<hubloc>:<port>"teachesusb_port_power_cycle(shared bybench_init.py/regress.py) to cut real VBUS via uhubctl for mapped DUTs, giving genuine first-plug cold per cell. Root ports must never be mapped (a root-port uhubctl cycle wedged a device on this rig beyond anything but a machine power-off).tests/cold_first_init_8812au.sh— the discriminator harness: per-rep VBUS cold, six arms (unit × rtw88-present/absent × retry/idle), flood verified radiating before and after every arm, mid-off port-power evidence captured.tests/bench_8812au_row.sh— the row measurement wrapper (handles two same-PID/same-serial units by powering the spare's port off, temp-blacklists rtw88_8812au, runsbench_init.pywith the VBUS map;WARM=1for the toggle-warm table).🤖 Generated with Claude Code