[WIP] Claude port plan for Sienna 1.0 by acostarelli · Pull Request #154 · Sienna-Platform/PowerOperationsModels.jl

acostarelli · 2026-06-29T00:17:49Z

G-1 contingencies in a separate PR.

Thanks for opening a PR to PowerOperationsModels.jl, please take note of the following when making a PR:

Gap analysis + actionable plan for porting PSI (PowerSimulations.jl) formulation changes, post-fork merged-PR code gaps, and the in-progress G-1 generator-contingency work (PSI open PR #1617) into POM. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

Bugfixes: - #1519 TwoTerminalHVDC AreaBalance add_to_expression! keys by PSY.Area (was PSY.ACBus) and uses HVDCTwoTerminalDispatch (fixes undefined refs) - #1527 drop spurious Float64 arg from round(..., RoundUp) in thermal duration - #1587 parallel/series interface-reduction errors now name offending branches Features: - #1549 Source default time-series names (+ skip-not-error when no device has TS) - #1573 FixedOutput Source constructor (+ multipliers, convert_output_to_natural_units) - #1538 renewable add_feedforward_arguments! + get_parameter_multiplier - #1605 AreaPTDF InterconnectingConverter injection (replaces error) - #1622 route reactive-power TS to AC PF on active-power-only network models (_add_pf_only_time_series_parameters!; thread template into add_power_flow_data!) - #1612 split In/Out storage/source headroom + in/out PF input keys/precedences (#1508, #1535, #1614, #1566 were already correct in POM.) Enable TransmissionInterface service templates: - uncomment _modify_device_model! no-ops for ConstantMaxInterfaceFlow / VariableMaxInterfaceFlow (both fully defined+exported in POM) - widen _is_interchanges_interfaces(::Dict) (was MethodError via Dict invariance) Tests: - new tests for #1573 / #1612 / #1622 - test_services_constructor 2 -> 16 testsets - test_network_constructors 1 -> 11 testsets Full suite: 23,695 pass. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

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Pull request overview

This PR ports a substantial set of PowerSimulations.jl formulation tests and missing formulation behaviors into PowerOperationsModels.jl, focused on reserves, transmission interfaces, in-the-loop power-flow input mapping (including split in/out active power), and several post-fork gaps for Sources, renewables, HVDC, and PTDF/AC power-flow integration.

Changes:

Port and adapt large test coverage for service constructors, network constructors, and power-flow-in-the-loop behaviors.
Add/extend formulation support for Source FixedOutput, renewable feedforward arguments, AreaPTDF interconnecting converter expressions, and interface/reduction error messages.
Extend PowerFlows extension input mapping to include split :active_power_in/:active_power_out channels and PF-only time-series parameter injection (e.g., reactive power TS on active-power-only network models).

Reviewed changes

Copilot reviewed 19 out of 19 changed files in this pull request and generated 3 comments.

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File	Description
test/test_services_constructor.jl	Ports/updates reserves + transmission interface test coverage with POM-stable assertions.
test/test_power_flow_in_the_loop.jl	Adds tests for split in/out active power mapping, headroom slack with in/out, and reactive power TS routing.
test/test_network_constructors.jl	Ports/extends network-constructor coverage across CopperPlate/PTDF/AreaBalance/AreaPTDF and reductions.
test/test_device_source_constructors.jl	Adds FixedOutput Source + time-series test coverage.
src/static_injector_models/thermal_generation.jl	Adjusts rounding call for time-limit discretization.
src/static_injector_models/source.jl	Adds FixedOutput multiplier methods and default Source TS-name mapping.
src/static_injector_models/source_constructor.jl	Implements Source `FixedOutput` construction path (parameter-only, no constraints).
src/static_injector_models/renewablegeneration_constructor.jl	Ensures renewable feedforward arguments are added in constructors.
src/static_injector_models/renewable_generation.jl	Adds `get_parameter_multiplier` for `VariableValueParameter` to support feedforwards.
src/operation/build_problem.jl	Threads the template into `add_power_flow_data!` to enable PF-only parameter injection.
src/mt_hvdc_models/HVDCsystems.jl	Implements AreaPTDF add-to-expression routing for `InterconnectingConverter`.
src/core/problem_template.jl	Adds no-op `_modify_device_model!` overloads for TransmissionInterface service models.
src/core/parameters.jl	Marks Source in/out TS parameters as convertible to natural units.
src/core/interfaces.jl	Extends `add_power_flow_data!` signature to accept an optional template.
src/common_models/add_to_expression.jl	Fixes TwoTerminalHVDC AreaBalance routing and improves interface/reduction errors.
src/common_models/add_parameters.jl	Changes missing time-series handling from error to informational skip.
ext/PowerFlowsExt/pf_input_mapping.jl	Adds PF input categories for split in/out active power and PF-only TS parameter injection.
ext/PowerFlowsExt/pf_headroom.jl	Adds in/out headroom accumulation logic and updates headroom recompute workflow.
.claude/pom_port_plan.md	Adds internal port-planning notes for PSI→POM workstreams.

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 get_multiplier_value(::Type{ActivePowerTimeSeriesParameter}, d::PSY.Source, ::Type{<:AbstractSourceFormulation}) = PSY.get_active_power_limits(d, PSY.SU).max
 get_multiplier_value(::Type{ActivePowerOutTimeSeriesParameter}, d::PSY.Source, ::Type{<:AbstractSourceFormulation}) = PSY.get_active_power_limits(d, PSY.SU).max
 get_multiplier_value(::Type{ActivePowerInTimeSeriesParameter}, d::PSY.Source, ::Type{<:AbstractSourceFormulation}) = PSY.get_active_power_limits(d, PSY.SU).max


+`net = p_out - p_in` is the device's signed contribution at time `t`. With net > 0 the
+device is dispatching and its headroom is `p_max_out - net`; with net <= 0 the device is
+charging (or idle) and contributes no upward slack.


+            # Net <= 0 means charging or idle — per spec, no upward slack contribution.
+            net < 0.0 && continue


Add a Progress block (per-workstream status, the two TransmissionInterface src enabling fixes, known gaps, test-port conventions) and annotate the suggested execution order to reflect what landed on ac/sienna1-port. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

Verified by symbol against origin/ac/sienna1-port + the PSI #1559/#1561 diffs: DLR is implemented as BranchRatingTimeSeriesParameter (reduction/ parallel-branch aware), tests present, PNM psy6 sufficient. The only un-ported PSI piece is the recurrent-solve _update_parameter_values! overload, which is Simulation/Emulation-scoped (out of POM scope). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

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Pull request overview

Copilot reviewed 29 out of 30 changed files in this pull request and generated 5 comments.

+  - `value::Float64`: value to compare to in p.u.
+"""
+struct StateVariableValueCondition <: AbstractEventCondition
+    variable_type::VariableType


 function get_default_time_series_names(
    ::Type{U},
    ::Type{V},
-) where {U <: PSY.Source, V <: AbstractSourceFormulation}
-    return Dict{Any, String}()
+) where {U <: PSY.Source, V <: Union{FixedOutput, AbstractSourceFormulation}}
+    return Dict{Type{<:TimeSeriesParameter}, String}(


    if isempty(device_names)
-        error(
-            "No devices with time series $ts_name found for $D devices. Check DeviceModel time_series_names field.",
-        )
+        @info "No devices with time series $ts_name found for $D devices. Skipping parameter addition."
+        return
    end


+            devices = IOM.get_available_components(device_model, sys)
+            isempty(devices) && continue
+            POM.add_parameters!(container, ParamT, devices, device_model)


PowerSystems 6 renamed TwoTerminalVSCLine's Bool control flags to scoped-enum control modes (dc_voltage_control_* -> dc_control_*/ac_control_* of type VSCDCControlModes/VSCACControlModes), and the pre-5.x keyword constructor can't be shimmed. Update _generate_test_vsc_sys to pass the *_VOLTAGE enum members (equivalent to the old `true`). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

acostarelli · 2026-07-13T23:57:47Z

Closing in favor of splitting this bundle into six focused, independently-reviewable PRs (each rebased onto current main, with the native-model rename and other API drift resolved):

Fix thermal min-up/down rounding and improve parallel-branch interface error messages #181 — Fix thermal min-up/down rounding and improve parallel-branch interface error messages
Add FixedOutput formulation for Source devices #182 — Add FixedOutput formulation for Source devices
Add feedforward arguments for renewable dispatch #183 — Add feedforward arguments for renewable dispatch
Enable TransmissionInterface service models #184 — Enable TransmissionInterface service models
Route reactive power and split in/out headroom to power-flow-in-the-loop #185 — Route reactive power and split in/out headroom to power-flow-in-the-loop
Support InterconnectingConverter under AreaPTDFNetworkModel #186 — Support InterconnectingConverter under AreaPTDFNetworkModel + network test coverage

Notes: the HVDC area-balance fix (#1519) and the VSC test-helper fix originally bundled here are already on main, so they were dropped. The Sienna port-plan document is not carried into any of the new PRs. PowerFlows stays pinned to psy6 (PowerFlows main is v0.23.0, which POM's [compat] excludes).

Anthony Costarelli and others added 2 commits June 25, 2026 18:10

acostarelli requested a review from Copilot June 29, 2026 00:17

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Anthony Costarelli and others added 2 commits June 28, 2026 20:30

acostarelli requested a review from Copilot June 29, 2026 03:16

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acostarelli changed the title ~~[WIP] Final ports for Sienna1.0~~ [WIP] Claude port plan for Sienna 1.0 Jun 29, 2026

acostarelli force-pushed the ac/sienna1-port branch from 09d7951 to 8bbeb3d Compare June 30, 2026 18:28

acostarelli force-pushed the ac/sienna1-port branch from a79c417 to 6acdbab Compare June 30, 2026 19:06

acostarelli closed this Jul 13, 2026

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[WIP] Claude port plan for Sienna 1.0#154

[WIP] Claude port plan for Sienna 1.0#154
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		# Net <= 0 means charging or idle — per spec, no upward slack contribution.
		net < 0.0 && continue

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acostarelli commented Jun 29, 2026 •

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