aclint

Core-local interrupts and timer: CLINT and ACLINT from one module, selected by feature.

Part of the Tape-Out IP library: Bluespec IP over the bus-neutral contracts in hwcore, assembled by xirang. Maturity runs planned -> simulated -> fpga-proven -> asic-ready -> silicon-proven.

Status

Planned. What sits in this repository today is the retired picorv32-era Verilog, kept for provenance; the Bluespec rewrite has not landed yet.

License

任选其一：

• MIT
• Apache 2.0
• 木兰宽松许可证 第2版

SPDX-License-Identifier: MIT OR Apache-2.0 OR MulanPSL-2.0

除非另行说明，你提交的贡献按上述三者同时授权，不附加其他条件。