hazard3

Luke Wren's Hazard3, the three-stage RV32 core used in the RP2350, taken as a black box.

Part of the Tape-Out IP library, wired up by xirang. One submodule, not modified: third_party/hazard3, on upstream's stable branch.

What this repository adds

The top is hazard3_cpu_2port, with an AHB5 manager port each for instructions and data, the debug module interface, the debugger's system bus access, the fence handshake and three interrupt inputs. The extensions, the CSR groups, U mode, debug support, the multiplier variants, the branch predictor, the PMP region count and the interrupt count are the knobs.

Upstream's RTL does not check its parameters against each other. Its configuration guide states one requirement per parameter ("Requires:"), and the manifest encodes each of them as a depends or a guard, with the guide's line number next to it. One more guard is ours: with the Xh3irq controller on, a single interrupt makes a zero-width encoder (hazard3_onehot_encode.v:21), although the guide gives 1 as the minimum.

$ ran test hazard3

Testing

Every point of the matrix runs upstream's riscv-tests (its own fork, as a nested submodule), the same flow as test/sim/riscv-tests/run-isa-tests.sh with two differences. The parameters come from the point instead of config_default.vh, and the testbench is upstream's Verilator one rather than CXXRTL, which g++ takes over ten minutes to compile per point. Suites follow the extensions: rv32uc only with C, rv32um with M, rv32ua with A, rv32mi with the trap CSRs. Two kinds of point skip the tests: RV32E, since the tests use registers above x15, and points without the mandatory machine CSRs, which upstream's guide calls "an absolute requirement for compliance with the RISC-V privileged specification" and which the test environment reads (mhartid) before anything else.

Tests that do not apply to a point are not run: zicntr and instret_overflow without the counters, pmpaddr without PMP regions, fence_i without Zifencei.

Two upstream defects are expected to fail, and the run turns red if either ever passes:

• With A on and Zbb off, which is upstream's default, amomaxu.w and amominu.w compare as signed. hazard3_alu.v treats MAXU and MINU as unsigned only when Zbb is on, though its result select already covers A.
• With U mode on and the counters off, mcounteren does not exist (hazard3_csr.v:991 requires both), while the privileged specification requires it in any hart with U mode (norm:mcounteren_flds_mandatory_warl). rv32mi-p-csr writes it as soon as it sees U mode.

Upstream's testbench enables every feature, so its own runs see neither.

Limits

The reset vector, the initial mtvec, the hardwired PMP regions and the ID registers stay at upstream's defaults. Zilsd, Zclsd and the Xh3bextm and Xh3pmpm extensions are not exposed yet.

License

This repository: 任选其一 MIT · Apache 2.0 · 木兰宽松许可证 第2版.

third_party/hazard3 stays under Apache-2.0; see its licence file.