Pulse-width modulator with configurable channels and dead time.
Part of the Tape-Out IP library: Bluespec IP over the
bus-neutral contracts in hwcore, assembled by
xirang. Maturity runs planned -> simulated ->
fpga-proven -> asic-ready -> silicon-proven.
Planned. What sits in this repository today is the retired picorv32-era Verilog, kept for provenance; the Bluespec rewrite has not landed yet.
开始采用：
- RO - READ ONLY
- WO - WRITE ONLY
- RW - READ WRITE
- TP - TEMP WIRE OR REG - DEFAULT - 默认不加
任选其一：
SPDX-License-Identifier: MIT OR Apache-2.0 OR MulanPSL-2.0
除非另行说明，你提交的贡献按上述三者同时授权，不附加其他条件。