This repository contains the research specifications, theoretical foundations, and architectural documentation for thermodynamic computing as the physical substrate layer of the Zae Project.
Project Status: conceptual research phase (TRL 2–3). No hardware exists in this repository. The repo documents theoretical architecture, identifies technology gaps, and maps the path from current research to brain scale emulation.
Note: thermodynamic computing at brain scale is a research frontier. Claims about energy efficiency and scaling represent theoretical limits and experimental projections, not validated production performance. Consult primary sources in
reference/bibliography.md.
Modern AI accelerators operate far above the thermodynamic lower bound of computation. Erasing one bit of information dissipates a minimum of
| Metric | Digital CMOS (Approx.) | Thermodynamic Ideal | Delta |
|---|---|---|---|
| Energy per operation |
|
|
|
| Signal-to-Noise Ratio | >1000:1 | ~1:1 | Inverted operating regime |
| Computation mechanism | Switching / clocking | Physical relaxation | n/a |
For the Zae Project specifically, the arkspace-core design targets 100M neurons per satellite node at 50–200W. This target is not reachable with von Neumann digital architectures. Thermodynamic computing performs computation by the natural relaxation of a physical stochastic substrate, which is the physical paradigm that makes the target conceivable.
Thermodynamic computing treats thermal noise as a computational resource rather than a source of error to be suppressed. A thermodynamic computer consists of physical degrees of freedom (voltages, magnetic moments, mechanical oscillators) whose dynamics are governed by the overdamped Langevin equation:
where
Inference, sampling, and optimization are core to spiking neural network operation, and they are formally identical to the natural dynamics of physical systems relaxing toward equilibrium. The substrate computes by physics, not by transistor switching.
The Zae Project has four interconnected pillars:
| Pillar | Repository | Layer | Role |
|---|---|---|---|
| 🛰️ Infrastructure | arkspace-core | Space | Where computation lives (LEO satellite constellation) |
| 🧠 Interface | brain-emulation | BCI | How bio↔synthetic connects (corpus callosum) |
| ⚡ Engine | neutral-consciousness-engine | Software | What runs (SNN, neural firewall) |
| 🌡️ Substrate | thermodynamic-core (this repo) | Physics | How it computes (stochastic physics, p-bits, Langevin) |
The Substrate layer sits beneath the Engine and is embedded in the Infrastructure's payload design. It defines the physical computing paradigm on which the Engine ultimately runs.
Per-pillar contracts live in docs/integration/:
with-arkspace.md. Orbital payload envelope (power, radiation, thermal).with-consciousness-engine.md. SNN → TC parameter transfer via Onsager-Machlup.with-brain-emulation.md. Atlas → TC energy-landscape mapping, shared benchmarks.
| Technology | Physical Principle | Advantage | Status |
|---|---|---|---|
| STT/SOT MTJ p-bits | Magnon-driven switching | Non-volatility, speed | Research |
| VCMA-MTJ p-bits | Electric-field anisotropy modulation | Ultra-low switching energy | Early R&D |
| Subthreshold CMOS | Thermal diffusion in subthreshold transistors | Standard fabrication process | Demonstrated |
| STL Neuristor | Single-transistor latch, CMOS-compatible | Stochastic + deterministic dual mode | Research |
| Josephson Junctions | Macroscopic quantum tunneling | High speed, high fidelity | Cryogenic only |
| THRML (JAX) | Software-to-hardware compiler | Bridges ML graphs to TC hardware | Actively developed |
The following gaps exist between current demonstrated technology and what is required for brain scale deployment on orbital hardware:
| Gap | Description | Path Forward |
|---|---|---|
| Radiation hardening | No radiation-hardened stochastic/TC chips demonstrated for LEO | Shielding + error-correcting architectures; long-term fab R&D |
| Integration complexity | MTJ p-bits require exotic materials (Heusler alloys, MgO barriers) not standard in CMOS fabs | All-transistor subthreshold CMOS as near-term substitute |
| Interconnect wall |
|
Hierarchical Bilinear Skip Coupling (rank-$k$ SVD approximation) |
| Input conditioning | Signal deficit of up to 2600× from fixed coupling constants in Langevin substrates | Minimal digital conditioning interface (<0.1% of model parameters) |
| Training at scale | Early TC designs required genetic algorithms; gradient-descent training only recently demonstrated | Whitelam (PNAS 2026) Onsager-Machlup functional approach |
| Thermal management in orbit |
|
Thermal isolation + operating temperature engineering |
thermodynamic-core/
├── README.md # This file
├── LICENSE # MIT
├── .gitignore
├── docs/
│ ├── architecture/
│ │ ├── theoretical-foundations.md # Stochastic thermodynamics, Langevin, EDDP
│ │ ├── hardware-primitives.md # p-bits: MTJ variants, subthreshold CMOS
│ │ ├── neuromorphic-integration.md # SSNN, STL neuristors, Spiking STDP Transformer
│ │ ├── scaling-interconnects.md # HBSC, eigenvalue concentration, digital conditioning
│ │ └── software-stack.md # THRML, compiler/ISA, graph lowering
│ ├── algorithms/
│ │ ├── dtm-and-dtca.md # Denoising Thermodynamic Models + Architecture
│ │ ├── thermodynamic-linear-algebra.md # K-FAC, natural gradient, matrix inversion
│ │ └── langevin-training.md # Whitelam framework, Onsager-Machlup
│ ├── protocols/
│ │ └── hybrid-digital-analog.md # Digital conditioning interface spec
│ └── integration/
│ ├── with-consciousness-engine.md # TC ↔ neutral-consciousness-engine
│ ├── with-arkspace.md # TC ↔ arkspace-core (orbital payload)
│ └── with-brain-emulation.md # TC ↔ brain-emulation (stochastic vs. deterministic)
├── reference/
│ └── bibliography.md # All primary TC sources
└── research/
└── technology-readiness.md # TRL matrix for TC components
| Phase | Scope | Status |
|---|---|---|
| Phase 1. Docs | Architecture specs, algorithm documentation, bibliography, cross-pillar integration contracts | Complete (April 2026) |
| Phase 2. Simulation | NumPy and JAX prototype simulations: Langevin integrator, p-bit sampler, thermodynamic linear algebra, Boltzmann machine, planned: Onsager-Machlup training, DTM/DTCA, K-FAC, HBSC | In progress (Step 2.1 of 7 landed 2026-04-22, 14/14 tests passing) |
| Phase 3. Integration | TC hardware specs for arkspace-core orbital payloads, radiation-hardened substrate design, uplink θ-update protocol, Neural Firewall extension | Future |
- arkspace-core, the orbital infrastructure that this substrate must eventually run on.
- neutral-consciousness-engine, the SNN engine that this substrate underlies.
- brain-emulation, the BCI interface layer.
- zae-docs, unified architecture documentation and bibliography.
All documentation changes should reference primary sources in reference/bibliography.md. Clearly distinguish between:
- Proven: Demonstrated in peer-reviewed literature or deployed hardware
- Speculative: Theoretical projections or early-stage R&D claims
See zae-docs for organization-wide contribution guidelines.
MIT. See LICENSE.