memory_array.v

`timescale 1ns / 1ps
`include "axi_pkg.vh"

module memory_array(

    input                           clk,
    input                           resetn,

    input                           write_en,
    input                           read_en,

    input   [`MEM_ADDR_WIDTH-1:0]   address,
    input   [`DATA_WIDTH-1:0]       write_data,

    output reg [`DATA_WIDTH-1:0]    read_data

);

//=========================================================
// Memory Declaration
//=========================================================

reg [`DATA_WIDTH-1:0] memory [0:`MEM_DEPTH-1];

integer i;

//=========================================================
// Memory Operations
//=========================================================

always @(posedge clk) begin

    if(!resetn) begin

        read_data <= 0;

        // Optional memory initialization
        for(i = 0; i < `MEM_DEPTH; i = i + 1)
            memory[i] <= 0;

    end

    else begin

              //-------------------------
        // Write Operation
        //-------------------------

        if (write_en) begin
            memory[address] <= write_data;
            $display("WRITE: addr=%0d data=%h", address, write_data);
        end

        //-------------------------
        // Read Operation
        //-------------------------

        if (read_en) begin
            read_data <= memory[address];
            $display("READ : addr=%0d data=%h", address, memory[address]);
        end

    end    // <-- closes the else begin

end        // <-- closes always block

endmodule