🚀 AMBA AXI4 Memory Controller

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📖 Overview

This project implements a simplified AMBA AXI4 Memory Controller in Verilog HDL, providing an interface between an AXI4-compliant master and an internal synchronous memory.

The controller features independent Read and Write Finite State Machines (FSMs), burst transaction handling, address generation logic, and a modular memory interface. The design follows the AXI4 VALID/READY handshake protocol and has been functionally verified through simulation in Xilinx Vivado.

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🎯 Objectives

• ✅ Implement an AXI4-compliant memory controller
• ✅ Design independent Read and Write FSMs
• ✅ Support burst-based memory transactions
• ✅ Interface an internal synchronous RAM
• ✅ Verify functionality through simulation
• ✅ Build a reusable RTL design

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✨ Features

• ✅ AXI4 Write Address Channel
• ✅ AXI4 Write Data Channel
• ✅ AXI4 Write Response Channel
• ✅ AXI4 Read Address Channel
• ✅ AXI4 Read Data Channel
• ✅ Independent Read & Write FSMs
• ✅ Incrementing Burst (INCR) Support
• ✅ Parameterized Design
• ✅ Internal Memory Interface
• ✅ Burst Counter
• ✅ Address Generation Logic
• ✅ AXI VALID/READY Handshake
• ✅ Simulation Testbench

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🏗️ Project Architecture

The design consists of three major blocks:

• 🔹 AXI4 Interface
• 🔹 Memory Controller
• 🔹 Internal Memory Array

The controller accepts AXI transactions, processes burst information, generates memory control signals, and returns protocol-compliant responses.

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📂 Project Structure

AMBA_AXI4_Memory_Controller
│
├── rtl/
│   ├── axi4_memory_controller.v
│   ├── memory_array.v
│   └── axi_pkg.vh
│
├── testbench/
│   └── tb_axi4_memory_controller.v
│
├── images/
│   ├── projectarchitecture.png
│   ├── WriteFSMdiagram.png
│   ├── ReadFSMDiagram.png
│   ├── memoryinterfacediagram.png
│   ├── schematic.png
│   └── waveform.png
│
└── README.md

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⚙️ Module Description

🧠 AXI4 Memory Controller

Responsible for:

• Address decoding
• Burst handling
• Read/Write FSM control
• Memory interface generation
• AXI response generation

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💾 Memory Array

Implements an internal synchronous RAM.

Functions include:

• Memory initialization
• Synchronous writes
• Synchronous reads
• 32-bit data storage

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🧪 Testbench

The verification environment performs:

• Reset generation
• Write transaction verification
• Read transaction verification
• Burst transfer testing
• Waveform analysis

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🔄 Write FSM

🟢 WR_IDLE

• Wait for AWVALID
• Capture address
• Store burst parameters

⬇️

🟡 WR_DATA

• Accept write data
• Generate memory write enable
• Increment address
• Update burst counter

⬇️

🔵 WR_RESP

• Generate write response
• Wait for BREADY
• Return to idle

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📖 Read FSM

🟢 RD_IDLE

• Wait for ARVALID
• Capture read address

⬇️

🟡 RD_MEM

• Generate memory read request

⬇️

🔵 RD_DATA

• Return read data
• Assert RVALID
• Complete transaction

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🔌 Memory Interface

Signal	Description
📍 mem_addr	Memory address
✍️ mem_write_en	Write enable
📖 mem_read_en	Read enable
📦 mem_write_data	Data written to RAM
📤 mem_read_data	Data returned from RAM

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📈 Burst Address Generation

The controller currently supports Incrementing Burst (INCR) transactions.

Next Address = Current Address + (1 << AWSIZE)

Example:

0x20
 ↓
0x24
 ↓
0x28
 ↓
0x2C

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🧪 Simulation

Simulation performed using:

• 🛠️ Xilinx Vivado 2022.2
• 🖥️ XSim Simulator

Verified functionality includes:

• ✅ Reset sequence
• ✅ AXI handshakes
• ✅ Write transactions
• ✅ Memory writes
• ✅ Burst counter
• ✅ Address increment
• ✅ Write responses
• ✅ Read request generation
• ✅ FSM transitions

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📊 Schematic

The waveform demonstrates:

• AXI VALID/READY handshaking
• Write state transitions
• Read state transitions
• Burst address updates
• Memory interface activity
• Internal RAM operations

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✔️ Verification Summary

Feature	Status
Reset	✅
Write Address	✅
Write Data	✅
Memory Write	✅
Burst Counter	✅
Address Increment	✅
Write Response	✅
Read Request	✅
FSM Operation	✅
Simulation	✅

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🚧 Current Limitations

The project demonstrates the core architecture and protocol flow of an AXI4 Memory Controller.

Current areas identified for future enhancement include:

• 🔸 Improved synchronization of memory read timing
• 🔸 Full support for FIXED and WRAP burst types
• 🔸 Byte-enable (WSTRB) implementation
• 🔸 AXI error response handling
• 🔸 Multiple outstanding transactions
• 🔸 Dual-port memory support
• 🔸 FPGA hardware validation

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🚀 Future Improvements

• 🔹 AXI4-Lite variant
• 🔹 Configurable memory depth
• 🔹 Configurable burst lengths
• 🔹 Dual-port RAM
• 🔹 ECC memory
• 🔹 Performance counters
• 🔹 SystemVerilog Assertions (SVA)
• 🔹 UVM Verification Environment
• 🔹 FPGA deployment

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📚 Learning Outcomes

This project strengthened practical understanding of:

• 💡 RTL Design
• 💡 Verilog HDL
• 💡 AMBA AXI4 Protocol
• 💡 Finite State Machines
• 💡 Burst Transactions
• 💡 Memory Controller Design
• 💡 Synchronous RAM
• 💡 Digital Verification
• 💡 Waveform Debugging

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🛠️ Tools & Technologies

Category	Tool
💻 HDL	Verilog
🖥️ Simulator	XSim
🛠️ IDE	Xilinx Vivado 2022.2
🌱 Version Control	Git
📂 Repository	GitHub

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👩‍💻 Author

Archita Roy

🎓 B.Tech in Electronics & Communication Engineering
🏛️ National Institute of Technology Silchar

GitHub: @archita-2005

📄 License

Licensed under the MIT License.

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🙏 Acknowledgements

This project was developed as part of my RTL Design and Computer Architecture portfolio to strengthen practical understanding of the AMBA AXI4 protocol, memory controller design, FSM-based control logic, and digital hardware verification.