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  • Boston, MA

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arsalansaif/README.md

Hi, I'm Arsalan Saif 👋

MS Electrical & Computer Engineering student focused on hardware engineering — the silicon behind intelligent systems, from embedded devices to high-performance chips. I like working close to the metal, and I'm especially interested in how compilers, memory systems, and CPU/GPU architectures shape real-world performance — and how those designs are verified before tape-out.

Currently focused on design verification and embedded systems, with a growing focus on computer architecture and memory systems for AI and HPC.

C C++ CUDA Verilog Python PyTorch

🔧 Skills

  • Hardware / VLSI: digital design, Verilog, design verification, embedded systems, sensor integration
  • Architecture & systems: CPU/GPU architecture, memory hierarchies & caches, CUDA, OpenMP, performance analysis
  • Languages: C, C++, Python, CUDA, Verilog
  • AI / ML: PyTorch, applied machine learning

💡 Experience highlight

Real-time pressure-mapping system — Penn State Health. Built from the ground up: embedded hardware, sensor integration, and wireless visualization, working under real clinical conditions. A hands-on reminder of how small hardware decisions ripple up into system-level behavior.

🚀 Featured projects

Project What it is
vlsi-16bit-multiplier-cadence Transistor-level 16-bit multiplier in Cadence Virtuoso (45 nm gpdk045) — CMOS gates → Booth-Wallace adder tree, Spectre-verified, Pegasus DRC
batched-fft-benchmark Hand-written batched 1D FFT in C++/OpenMP & CUDA, benchmarked vs. Intel MKL and cuFFT on P100/V100 GPUs — with roofline & memory-bandwidth analysis
design-exploration 18-dimensional CPU design-space exploration in SimpleScalar, optimizing for execution time and energy efficiency
cache-simulator Configurable set-associative CPU cache simulator in C (variable size / associativity / block size, LRU)
cordic-signal-processor CORDIC-based signal processor — complex FIR filter + Cartesian→polar rotator, built with HLS pipeline/unroll pragmas
five-stage-pipelined-cpu-verilog Five-stage pipelined CPU (IF/ID/EX/MEM) in Verilog for Xilinx FPGAs
mapreduce-wordcount-c Multithreaded MapReduce-style word count in C with a bounded producer–consumer buffer
taxi-driver-trajectory-lstm PyTorch LSTM for GPS trajectory sequence classification (applied ML)

📫 Reach me

Pinned Loading

  1. batched-fft-benchmark batched-fft-benchmark Public

    Hand-written batched 1D FFT (Cooley-Tukey radix-2) in C++/OpenMP and CUDA, benchmarked against Intel MKL and cuFFT on NVIDIA P100/V100 GPUs

    C++

  2. cache-simulator cache-simulator Public

    Configurable set-associative CPU cache simulator in C (variable cache size, associativity, and block size)

    C

  3. cordic-signal-processor cordic-signal-processor Public

    CORDIC-based signal processor: complex FIR filter + CORDIC rotator (Cartesian to polar magnitude/phase) with HLS pipeline/unroll/array-partition pragmas

  4. five-stage-pipelined-cpu-verilog five-stage-pipelined-cpu-verilog Public

    First four stages (IF/ID/EX/MEM) of a five-stage pipelined CPU designed and tested in Verilog for Xilinx FPGAs (Vivado)

  5. design-exploration design-exploration Public

    Design-space exploration over an 18-dimensional CPU design space (SimpleScalar), optimizing for execution time and energy efficiency

    C++

  6. vlsi-16bit-multiplier-cadence vlsi-16bit-multiplier-cadence Public

    Transistor-level 16-bit Booth-Wallace multiplier in Cadence Virtuoso (45nm gpdk045): CMOS gates to adder tree, Spectre-verified, Pegasus DRC

    Shell