Dev sdcard

.gitmodules

@@ -1,12 +1,12 @@
 [submodule "cpu/lib/am1802-csl"]
 	path = cpu/lib/am1802-csl
-	url = ../am1802-csl
+	url = https://github.com/bangcorrupt/am1802-csl
 [submodule "cpu/src/lib/UGUI"]
 	path = cpu/lib/UGUI
-	url = ../UGUI.git
+	url = https://github.com/bangcorrupt/UGUI.git
 [submodule "dsp/src/lib/aleph-dsp"]
 	path = dsp/lib/aleph-dsp
-	url = ../aleph-dsp.git
+	url = https://github.com/bangcorrupt/aleph-dsp.git
 [submodule "cpu/lib/LEAF"]
 	path = cpu/lib/LEAF
-	url = ../LEAF.git
+	url = https://github.com/bangcorrupt/LEAF.git

clean.sh

@@ -0,0 +1 @@
+sudo docker-compose exec freetribe make clean

cpu/lib/am18x/Makefile

@@ -0,0 +1,10 @@
+# tary, 0:49 2013/4/15
+
+all : am18x_map_s.h
+
+am18x_map_s.h: am18x_map.h
+	sed -n -e "/^#define/{ s/\([^0]0x[0-9a-fA-F]\+\)UL/\1/g;p; }" $< > $@
+
+clean:
+
+.PHONY: all clean

cpu/lib/am18x/am18x_aintc.h

@@ -0,0 +1,30 @@
+// tary, 0:01 2013/3/9
+
+#ifndef __AM18X_AINTC_H__
+#define __AM18X_AINTC_H__
+
+#include "am18x_map.h"
+
+typedef enum {
+	AINTC_GLOBAL,
+	AINTC_HOST_FIQ,
+	AINTC_HOST_IRQ,
+} aintc_host_t;
+
+typedef struct {
+	uint32_t	isr_addr;
+	uint32_t	isr_size;
+} aintc_conf_t;
+
+#define AINTC_INVALID_ACTIVE		(-1)
+
+am18x_rt aintc_conf(const aintc_conf_t* conf);
+am18x_rt aintc_enable(aintc_host_t host);
+am18x_rt aintc_disable(aintc_host_t host);
+am18x_rt aintc_sys_enable(AINTC_assign_t assign);
+am18x_rt aintc_sys_disable(AINTC_assign_t assign);
+am18x_rt aintc_trigger(AINTC_assign_t assign);
+am18x_rt aintc_clear(AINTC_assign_t assign);
+int32_t	 aintc_get_active(void);
+
+#endif//__AM18X_AINTC_H__

cpu/lib/am18x/am18x_conf.h

@@ -0,0 +1,88 @@
+// tary, 1:05 2012/12/23
+#ifndef __AM18X_CONF_H__
+#define __AM18X_CONF_H__
+
+#define __USE_STDINT_H
+
+//#include <am18x_type.h>
+#include <stdint.h>
+
+#define F_OSCIN			24000000UL	//Hz
+extern const uint32_t f_osc;
+
+#define _MPU
+#define _MPU1
+#define _MPU2
+
+#define _DCLK
+
+#define _PLL
+#define _PLL0
+#define _PLL1
+
+#define _PSC
+#define _PSC0
+#define _PSC1
+
+#define _SYSCFG
+#define _SYSCFG0
+#define _SYSCFG1
+
+#define _AINTC
+
+#define _PRU
+#define _PRU0
+#define _PRU1
+
+#define _DDR
+#define _DDR0
+
+#define _EDMA
+#define _EDMA0
+#define _EDMA1
+
+#define _GPIO
+
+#define _I2C
+#define _I2C0
+#define _I2C1
+
+#define _LCD
+#define _LCD0
+
+#define _MMCSD
+#define _MMCSD0
+#define _MMCSD1
+
+#define _TIMER
+#define _TIMER0
+#define _TIMER1
+#define _TIMER2
+#define _TIMER3
+
+#define _UART
+#define _UART0
+#define _UART1
+#define _UART2
+
+#define _USB
+#define _USB0
+
+#define _RTC
+
+#define _ECAP
+#define _ECAP2
+
+#ifdef DEBUG
+#define assert(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+#define assert(expr) ((void)0)
+#endif // DEBUG
+
+typedef void (*none_arg_handler_t)(void);
+
+int isr_set_handler(int intr_nr, none_arg_handler_t handle);
+
+
+#endif//__AM18X_CONF_H__

cpu/lib/am18x/am18x_dclk.h

@@ -0,0 +1,134 @@
+// tary, 19:03 2013/4/20
+
+#ifndef __AM18X_DCLK_H__
+#define __AM18X_DCLK_H__
+
+#include "am18x_map.h"
+
+typedef enum {
+	CLK_NODE_INVALID,
+
+	CLK_NODE_PLL0_SYSCLK1,
+	CLK_NODE_PLL0_SYSCLK2,
+	CLK_NODE_PLL0_SYSCLK3,
+	CLK_NODE_PLL0_SYSCLK4,
+	CLK_NODE_PLL0_SYSCLK5,
+	CLK_NODE_PLL0_SYSCLK6,
+	CLK_NODE_PLL0_SYSCLK7,
+	CLK_NODE_EMA_CLKSRC,
+	CLK_NODE_PLL0_AUXCLK,
+	CLK_NODE_PLL0_OBSCLK,
+	CLK_NODE_PLL1_SYSCLK1,
+	CLK_NODE_PLL1_SYSCLK2,
+	CLK_NODE_PLL1_SYSCLK3,
+	CLK_NODE_PLL1_OBSCLK,
+
+	CLK_NODE_ASYNC3,
+
+	CLK_NODE_PLL0_PLLEN,
+	CLK_NODE_PLL_EXTSRC,
+	CLK_NODE_POSTDIV0,
+	CLK_NODE_PLLM0,
+	CLK_NODE_PREDIV0,
+	CLK_NODE_PLL_CLKMODE,
+
+	CLK_NODE_DIV4_5X,
+	CLK_NODE_DIV4_5,
+
+	CLK_NODE_OSCDIV0,
+	CLK_NODE_OCSEL0_OCSRC,
+
+	CLK_NODE_PLL1_PLLEN,
+	CLK_NODE_POSTDIV1,
+	CLK_NODE_PLLM1,
+
+	CLK_NODE_OSCDIV1,
+	CLK_NODE_OCSEL1_OCSRC,
+
+	CLK_NODE_OSCIN,
+	CLK_NODE_CNT,
+} clk_node_id_t;
+
+typedef uint32_t (*pll_calc_freq_t) (uint32_t parent);
+
+typedef struct {
+	cuint32_t	id;
+	const char*	name;
+	uint32_t	parent;
+#define CN_FLAG_DIV			0x00000001UL
+#define CN_FLAG_MULT			0x00000002UL
+#define CN_FLAG_MULTI_DIV		0x00000003UL
+#define CN_FLAG_MUX			0x00000004UL
+#define CN_FLAG_REREAD			0x00000008UL
+#define CN_FLAG_RECALC			0x00000010UL
+#define CN_FLAG_VISITED			0x00000020UL
+	uint32_t	flag;
+	uint32_t	multiplier;
+	uint32_t	divider;
+	pll_calc_freq_t	calc_freq;
+	pll_calc_freq_t do_change;
+	uint32_t*	parent_list;
+	uint32_t	freq;
+} clk_node_t;
+
+#define DCLK_ID_GRP_SZ			0x100
+typedef enum {
+	DCLK_ID_ARM_RAM_ROM = CLK_NODE_PLL0_SYSCLK2 * DCLK_ID_GRP_SZ,
+	DCLK_ID_ON_CHIP_RAM,
+	DCLK_ID_UART0,
+	DCLK_ID_EDMA,
+	DCLK_ID_SPI0,
+	DCLK_ID_MMC_SDS,
+	DCLK_ID_VPIF,
+	DCLK_ID_LCDC,
+	DCLK_ID_SATA,
+	DCLK_ID_UPP,
+	DCLK_ID_DDR2_MDDR,
+	DCLK_ID_USB2_0,
+	DCLK_ID_HPI,
+	DCLK_ID_PRUSS,
+
+	DCLK_ID_EMIFA = CLK_NODE_EMA_CLKSRC * DCLK_ID_GRP_SZ,
+
+	DCLK_ID_SYSCFG = CLK_NODE_PLL0_SYSCLK4 * DCLK_ID_GRP_SZ,
+	DCLK_ID_GPIO,
+	DCLK_ID_PLLCS,
+	DCLK_ID_PSCS,
+	DCLK_ID_I2C1,
+	DCLK_ID_EMAC_MDIO,
+	DCLK_ID_USB1_1,
+	DCLK_ID_ARM_INTC,
+
+	DCLK_ID_ARM = CLK_NODE_PLL0_SYSCLK6 * DCLK_ID_GRP_SZ,
+
+	DCLK_ID_EMAC_RMII = CLK_NODE_PLL0_SYSCLK7 * DCLK_ID_GRP_SZ,
+
+	DCLK_ID_I2C0 = CLK_NODE_PLL0_AUXCLK * DCLK_ID_GRP_SZ,
+	DCLK_ID_TIMER64P0,
+	DCLK_ID_TIMER64P1,
+	DCLK_ID_RTC,
+	DCLK_ID_USB2_0_PHY,
+	DCLK_ID_MCASP0_SCLK,
+
+	DCLK_ID_DDR2_MDDR_PHY = CLK_NODE_PLL1_SYSCLK1 * DCLK_ID_GRP_SZ,
+
+	DCLK_ID_ECAPS = CLK_NODE_ASYNC3 * DCLK_ID_GRP_SZ,
+	DCLK_ID_UART1,
+	DCLK_ID_UART2,
+	DCLK_ID_TIMER64P2,
+	DCLK_ID_TIMER64P3,
+	DCLK_ID_EHRPWMS,
+	DCLK_ID_MCBSPS,
+	DCLK_ID_MCASP0,
+	DCLK_ID_SPI1,
+} dev_clk_id_t;
+
+am18x_rt clk_node_init(void);
+am18x_rt clk_node_output(void);
+am18x_rt clk_node_tree(void);
+am18x_rt clk_node_recalc(void);
+uint32_t clk_node_get_freq(uint32_t id);
+am18x_rt clk_node_set_parent(uint32_t id, uint32_t parent);
+uint32_t dev_get_freq(uint32_t dclk_id);
+
+#endif//__AM18X_DCLK_H__

cpu/lib/am18x/am18x_ddr.h

@@ -0,0 +1,45 @@
+// tary, 23:50 2013/10/27
+
+#ifndef __AM18X_DDR_H__
+#define __AM18X_DDR_H__
+
+#include "am18x_map.h"
+
+typedef struct {
+	uint8_t		ddr2_not_mddr;
+	uint8_t		page_size;	// 8..11
+	uint8_t		row_size;	// 9..16
+	uint8_t		bank_cnt;	// 1,2,4,8
+
+	uint32_t	freq_ck;
+	uint32_t	trefi;		// ns
+
+	uint8_t		cl;		// 2..3
+	uint8_t		trfc;		// ns
+	uint8_t		trp;		// ...
+	uint8_t		trcd;
+
+	uint8_t		twr;
+	uint8_t		tras;
+	uint8_t		trc;
+	uint8_t		trrd;
+
+	uint8_t		twtr;
+	uint8_t		todt;
+	uint8_t		txsnr;
+	uint8_t		trtp;
+
+	uint8_t		txp;		// tck
+	uint8_t		txsrd;		// tck
+	uint8_t		tcke;		// tck
+
+	uint32_t	trasmax;
+
+	uint8_t		pasr;
+} ddr_conf_t;
+
+am18x_rt ddr_initialize(DDR_con_t* dcon, const ddr_conf_t* conf);
+am18x_rt ddr_clock_off(DDR_con_t* dcon);
+am18x_rt ddr_clock_on(DDR_con_t* dcon);
+
+#endif//__AM18X_DDR_H__

cpu/lib/am18x/am18x_ecap.h

@@ -0,0 +1,25 @@
+// tary, 20:42 2017/6/20
+
+#ifndef __AM18X_ECAP_H__
+#define __AM18X_ECAP_H__
+
+#include "am18x_map.h"
+
+typedef enum {
+	ECAP_DISABLE = 0,
+	ECAP_ENABLE = BIT(0),
+	ECAP_ACTIVE_LOW = 0,
+	ECAP_ACTIVE_HIGH = BIT(1),
+} ecap_cflag_t;
+
+typedef struct {
+	uint32_t	freq;
+	uint32_t	duty;
+	uint8_t		cflags;
+} ecap_conf_t;
+
+am18x_rt ecap_init(ECAP_con_t* econ);
+am18x_rt ecap_get_conf(ECAP_con_t* econ, ecap_conf_t* conf);
+am18x_rt ecap_set_conf(ECAP_con_t* econ, const ecap_conf_t* conf);
+
+#endif//__AM18X_ECAP_H__