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馃懢
Sapere aude.
馃懢
Sapere aude.

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@cad-polito-it

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franout/README.md

Hi there, I'm Francesco 馃憢

Embedded Software Engineer 路 EDA/CAD Engineer 路 PostDoc researcher @ Politecnico di Torino

I work where software meets silicon, and how they interlace.

As a PostDoc, in collaboration with industrial partners, I develop functional test methodologies that detect manufacturing defects in high-end processors, build software-based safety mechanisms for safety-critical systems, and design and automate EDA flows for hardware test.

My PhD thesis, "System-Level Test Techniques for Automotive SoCs", developed methods to generate and grade system-level tests for large automotive chips.


馃О Tech stack

Languages

C C++ Python Bash TCL Assembly RISC-V

Hardware design & verification

VHDL Verilog SystemVerilog Chipyard Gem5

Embedded platforms

STM32 Arm FPGA RTOS

EDA / CAD tools

  • Synopsys: Design Compiler 路 TestMAX (TetraMAX) 路 VC Z01X (Z01X) 路 VCS 路 Verdi 路 PrimeTime
  • Cadence: Innovus 路 Incisive

DevOps & workflow

Linux Ansible Git GitHub GitLab


馃搳 GitHub stats

franout's GitHub stats Top languages


馃摣 Get in touch

LinkedIn Google Scholar ORCID Email

Off the keyboard: 馃ゾ trekking 路 馃嵎 wine tasting 路 馃殫 old car restoration

Pinned Loading

  1. cad-polito-it/testyard cad-polito-it/testyard Public

    Forked from ucb-bar/chipyard

    A dynamic RISC-V-based benchmarks generator for VLSI hardware testing

    Scala 1

  2. cad-polito-it/hammer cad-polito-it/hammer Public

    Forked from ucb-bar/hammer

    Hammer: Highly Agile Masks Made Effortlessly from RTL

    Python 2

  3. PTLIX PTLIX Public

    Portable Test Library Interface for different RTOSs and Software Test Libraries

    C

  4. Cogitantium Cogitantium Public

    Hardware Accelerator for ML

    VHDL 5 1

  5. freertos_meets_riscv freertos_meets_riscv Public

    A RISCV implementation of freeRTOS for Comet Simulator

    C

  6. micrium_meets_riscv micrium_meets_riscv Public

    A RISCV implementation of uC-OSIII for Comet Simulator

    C 1