I just cant get across.I read the Verlilog.If I'm not mistaken, in your Verilog code, you've implemented the write portion using a variable named bytecnt to achieve receiving 16-bit data at a time, but it's directly set to 1. However, the transmitting side still sends 16 bits at a time. According to this logic, it would send a single byte of data twice. Is this really the intended design?
I just cant get across.I read the Verlilog.If I'm not mistaken, in your Verilog code, you've implemented the write portion using a variable named bytecnt to achieve receiving 16-bit data at a time, but it's directly set to 1. However, the transmitting side still sends 16 bits at a time. According to this logic, it would send a single byte of data twice. Is this really the intended design?