Nord PCIe changes - #914
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Add qcom,glymur-qmp-gen5x8-pcie-phy.yaml as a standalone binding for the Glymur Gen5 PCIe PHY hardware block. This block supports two link modes, selected at runtime via a TCSR syscon register: 1. x8 - a single 8-lane PHY instance is exposed 2. x4+x4 - two independent 4-lane PHY instances are exposed Keep this as a separate schema from qcom,sc8280xp-qmp-pcie-phy.yaml rather than folding it into the shared compatible list there, since the two PHY instances active in x8 mode require twice as many clocks, resets, and power-domains as any other entry in that file, and adding Glymur-specific properties like qcom,link-mode and reg-names there would only apply to this one compatible. Document the required clocks, resets, and power-domains for both PHY instances, and use #phy-cells = <1>, where the cell value is the PHY index within the active link mode. Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Some QMP PCIe PHY hardware blocks support multiple link topologies (e.g. x8 or x4+x4) selected via a TCSR register. The existing single-instance QMP PCIe PHY driver has no way to model this: it assumes a single cfg per DT node and instantiates exactly one PHY. Add a dedicated driver for this class of PHY. Match data carries a per-mode cfg table; qmp_pcie_multiphy_probe() reads the current link mode from the TCSR register pointed to by "qcom,link-mode", looks up the corresponding cfg array, and instantiates one qmp_pcie per sub-PHY required by that link mode, registering the clock and #phy-cells = <1> phy providers so consumers can address individual sub-PHYs by index. The driver inherits the phy setting and link-mode programmed by firmware, so only the no_csr reset is used and no phy setting tables are provided. Add the first match data and compatible, qcom,glymur-qmp-gen5x8-pcie-phy, for the Glymur Gen5 PCIe PHY that can bifurcate into two x4 links or operate as a single x8 link. Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Add qcom,nord-qmp-pcie-phy.yaml as a standalone binding for the Nord (SA8797P) QMP PCIe PHY hardware block. This is a single bifurcated PHY with four independently-configurable lane segments (A/B/C/D) that can be ganged into different link-mode configurations at boot time via a TCSR syscon register: Mode 0 (x16) — all four segments ganged as a single x16 PHY Mode 1 (x8+x8) — segment A (x8) + segments B+C+D ganged (x8) Mode 2 (x8+x4+x4) — segment A (x8) + segment B (x4) + segments C+D (x4) Mode 3 (x8+x4+x2+x2) — four independent instances (x8/x4/x2/x2) Document the required clocks, resets, power-domains, and supplies for all four segments. Use #phy-cells = <1> to select the PHY instance by segment index (0–3). Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Add qcom,pcie-nord as a compatible variant of the SA8775P PCIe controller binding. Nord uses the SA8775P controller IP as a fallback compatible, with the primary compatible being qcom,pcie-nord. This allows the binding to validate Nord PCIe nodes that declare both compatibles. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
…tion
Add complete PCIe subsystem support for Nord (SA8797P) including:
- PCIe SMMU (System MMU) node for IOMMU support
- PCIe PHY node (pcie_phy) with bifurcated QMP configuration supporting
four independently-configurable lane segments (A/B/C/D) that can be
ganged into different link-mode configurations via TCSR syscon register
- Four PCIe controller nodes (pcie0–pcie3) with full clock, reset, power
domain, interrupt, and interconnect configuration
- PCIe root port child nodes (pcie{0-3}_port0) with PCI bridge compatible
- Pinctrl states in &tlmm for all four PCIe controllers with clkreq, perst,
and wake pin definitions
The PHY is wired to GCC as a clock provider for the four pipe clocks
(pcie_{a,b,c,d}_pipe_clk). Each PCIe controller is assigned its own
AUX clock rate (19.2 MHz) via assigned-clocks.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Enable all four PCIe controllers (pcie0–pcie3) and the PCIe PHY on the Nord RRD (Reference Reference Design) board. Configure PHY power supplies for all four segments (A/B/C/D) and set reset GPIO pins for each PCIe root port. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Add clk_nord_regs_configure() to set force_mem_core and force_periph_on
bits for all four PCIe pipe clocks (pcie_{a,b,c,d}_pipe_clk). These bits
ensure the pipe clocks remain active during low-power states, which is
required for proper PCIe link operation.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Add cgc_dis_workaround configuration flag to handle a timing-convergence issue in the power domain on some SA8775P-family instances (e.g. Nord). When enabled, set PARF_SYS_CTRL CORE_CLK_CGC_DIS and AUX_PWR_DET bits during post-initialization to work around the issue. The SLV_ACLK_CGC_DIS bit is already set by POR; this additionally sets CORE_CLK_CGC_DIS and AUX_PWR_DET as required by QCTDD11972446. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Move hardcoded QPHY_V8_50_PCS_* register offsets from direct usage to a generic register layout structure. This makes the code more maintainable and allows different PHY variants to define their own register layouts. Changes: - Create Nord-specific header (phy-qcom-qmp-pcs-v8_50-nord.h) with generic register layout enum (QPHY_PCS_STATUS, QPHY_PCS_START_CONTROL, QPHY_PCS_SW_RESET, QPHY_PCS_POWER_DOWN_CONTROL) - Add Nord-specific register layout array mapping enum to actual offsets - Update driver code to use cfg->regs[QPHY_PCS_*] instead of hardcoded constants in qmp_pcie_init_seg_registers(), qmp_pcie_power_on(), qmp_pcie_power_off(), and qmp_pcie_exit() - Keep Glymur using generic pciephy_v8_50_regs_layout with only QPHY_PCS_STATUS (no pll_tbls, so other registers not accessed) Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
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