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Add Nord Camss Support - #915

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Wenmeng Liu (wenmliu) wants to merge 6 commits into
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wenmliu:nord
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Add Nord Camss Support#915
Wenmeng Liu (wenmliu) wants to merge 6 commits into
qualcomm-linux:staging/nordfrom
wenmliu:nord

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Add the device tree bindings for the camera subsystem (CAMSS) found on
the Qualcomm Nord SoC.

Nord's CAMSS is a gen4 Titan ISP built from 5 CSIPHY (v2.4.0), 3 CSID
plus 10 CSID lite, and 3 IFE (VFE full) plus 10 IFE lite blocks. The
CSID full/lite blocks use the "900" register layout and the IFE blocks
reuse the gen4 VFE programming model.

Each CSIPHY has its own pair of 0.8V/1.2V supplies as the rails can
differ per sensor.

Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Add the CAMSS_NORD version and the "qcom,nord-camss" compatible for the
Nord camera subsystem. Nord is a gen4 Titan ISP based on Kaanapali.

Nord has 5 CSIPHY (v2.4.0), which is already supported in-tree, so only
a CAMSS_NORD entry in the shared switch-cases in camss-csiphy-3ph-1-0.c
is required and no new CSIPHY register code is added.

Unlike Kaanapali and SM8750, Nord has no CPAS clocks. It uses the
CORE_AHB/TOP_FAST_AHB interface clocks and the split IFE
MAIN/PCP/SCALAR/TMC plus per-IFE TOP_IFE clock tree.

The CSID, VFE and TPG resource tables are added in the following
patches.

Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Nord uses TPG v2.5.0, which moves the stream enable and reset out of
TPG_CTRL/TPG_CLEAR into a dedicated command register (TPG_CTRL_CMD) at
the same 0x1F4 offset. Branch tpg_stream_on() on the runtime hw_version:
revisions before v2.5.0 use the TPG_CTRL.TEST_EN bit, while v2.5.0
enables the generator through TPG_CTRL_CMD.TEST_EN.

The reset bit stays at bit 0 of the 0x1F4 register on every revision, so
tpg_reset() needs no version check; it also runs before the hardware
version is read.

Preserve the CFA pattern size (SIZE_X/SIZE_Y) at its reset value in
TPG_COLOR_BARS_CFG_STANDARD. Writing only ROTATE_PERIOD zeroed those
fields and reduced the pattern to 1x1, producing no valid output.

Add the Nord TPG resource table (tpg_res_nord) to nord_resources.

Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Add a CSID driver for the "900" revision on the Nord SoC.

CSID 900 shares the gen4 CSI-2 RX helpers and the split RUP/AUP command
model of CSID 980, where an explicit SET is required after programming
the AUP/RUP registers. Unlike CSID 980 it uses a single register map for
both the full and lite instances; only the RDI region base differs (full
at 0x1300, lite at 0x600, 0x200 stride). CSID 980 forks the lite layout,
so add a separate file rather than an IS_CSID_900() variant.

Nord has no test pattern generator wired to the CSID, so the testgen
path is a no-op, as on the other gen4 platforms.

Add the Nord CSID resource table (csid_res_nord) to nord_resources.

Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
The Nord IFE (VFE) reuses the gen4 VFE ops but places the bus write
master register block at a different base and drops one register. Add an
IS_VFE_900() variant in camss-vfe-gen4.c to handle the differences from
the existing gen4 (980/1080) layout:

  - BUS_REG_BASE is 0xA00 for VFE full and 0x700 for VFE lite.
  - There is no WM_CGC_OVERRIDE register, so the clock-gating override
    write is skipped.
  - TEST_BUS_CTRL moves to the head of the bus write master block
    (BUS_REG_BASE - 0x1BC) instead of BUS_REG_BASE + 0x128.
  - ADDR_IMAGE takes a full byte address instead of the 256-byte-unit
    (addr >> 8) encoding, and the full-IFE RDI write-master clients start
    at index 28 (0x1C) instead of 0x17.

All other write-master register offsets match gen4 and are reused
unchanged.

Add CAMSS_NORD to the shared VFE switch-cases and the Nord VFE resource
table (vfe_res_nord) to nord_resources.

Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Add the camera subsystem node for the Nord SoC with its 5 CSIPHY, 3 CSID
plus 10 CSID lite and 3 IFE plus 10 IFE lite blocks, along with their
clocks, interrupts, interconnects, SMMU stream IDs and power domains.

The node is enabled at the SoC level with the CSIPHY input ports left as
empty stubs. Each board fills in the port endpoints and CSIPHY supplies
for its on-board sensors.

Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
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