A pipelined Symmetric FIR (Finite Impulse Response) filter implementation in Verilog HDL.
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Updated
Dec 29, 2024 - Verilog
A pipelined Symmetric FIR (Finite Impulse Response) filter implementation in Verilog HDL.
MATLAB project that designs a first-order low-pass and high-pass FIR filter directly from their Z-domain transfer functions, then verifies each three ways — frequency response, pole-zero map, and impulse response — with a stability check via pole locations.
An adaptive filter design project that implements the Least Mean Squares (LMS) algorithm and compares its performance with conventional FIR filters using Hamming, Hanning, and Blackman window techniques.
This project discusses the evaluation of FIR filter coefficients using genetic algorithm, where multiple parameters are used to evaluate the filter coefficients given some design specifications in comparison with the famous windowing method as well as the Parks-McClellan algorithm as benchmarks.
A MATLAB-based pipeline for high-speed frame processing, featuring ADC conversion, polyphase decimation, and spectral analysis of low SNR signals.
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