nasdaq-itch
Here are 59 public repositories matching this topic...
Production-grade low-latency FPGA trading system. Features custom VHDL 10GBASE-R PHY, hardware NASDAQ ITCH 5.0 order book, C++ DPDK/XDP kernel bypass, and PCIe DMA acceleration. LLM-Inference
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May 24, 2026 - VHDL
MeatPy
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Aug 9, 2026 - Python
Finance and Trading Protocols in Golang
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Mar 2, 2026 - Go
Price response function and spread impact analysis in correlated financial markets
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Jan 13, 2025 - Jupyter Notebook
FPGA Nasdaq ITCH 5.0 feed handler and pipelined order book for the ZCU106, targeting 10GbE low-latency market data processing.
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Sep 21, 2026 - Python
Hardware-accelerated (FPGA) HFT trading pipeline for NASDAQ TotalView-ITCH 5.0 market data. Implements an async FIFO, MoldUDP64 deframer, ITCH parser, L1/L2/L3 limit order book, and trade signal engine. SystemVerilog RTL verified in Verilator against a C++ golden model and running on a Xilinx ZCU104 at 240 MHz with 33 ns decision latency.
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Sep 19, 2026 - C++
Nasdaq TotalView-ITCH 5.0 Parser
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Jul 27, 2026 - Python
Market Data Feed Handler, ITCH Protocol. MoldUDP Multicast Useful for the new Mexican Stock Exchange BIVA (Bolsa Institucional de Valores) that uses X-Stream (NASDAQ).
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Dec 18, 2018 - Java
BIVA MarketData ITCH Feed Handler Unicast SoupBinTCP BIVA MarketData ITCH Feed Handler Multicast MoldUDP BIVA MarketData ITCH Feed Handler Recovery UDP BIVA OrderRouting OUCH OMS Unicast SoupBinTCP BMV MarketData INTRA Feed Handler Multicast UDP BMV MarketData INTRA Feed Handler Recovery TCP Useful for the new Mexican Stock Exchange BIVA (Bolsa …
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Oct 16, 2018 - Java
Nasdaq OUCH 5.0 C libary
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Jun 25, 2024 - C
Parser for Nasdaq TotalView-ITCH 5.0
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Jan 10, 2020 - Python
Market Data Feed Handler, ITCH Protocol. SoupBinTCP Unicast Useful for the new Mexican Stock Exchange BIVA (Bolsa Institucional de Valores) that uses X-Stream (NASDAQ).
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Oct 15, 2018 - Java
High-performance PCAP market-data decoder for exchange feeds, currently focused on NASDAQ TotalView-ITCH 5.0 and multi-symbol Level-3 order book reconstruction.
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Sep 19, 2026 - C++
An ultra-low latency, O(1) limit order book written in C++20. Features zero-copy PCAP/ITCH network ingestion, lock-free ring buffers, and custom memory pools to achieve ~9ns per-order matching latency.
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Aug 6, 2026 - C++
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