scan-dff

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snehanjali24 / 4-bit-ALU-with-Scan-Based-DFT-Verification

Designed and verified a Scan-Enabled 16-Operation 4-Bit ALU using Verilog HDL. Implemented a 4-stage scan chain using scan flip-flops and developed a self-checking testbench to verify all ALU operations and scan-shift functionality in Vivado.

dft verilog vivado vlsi yosys digital-design design-verification rtl-design scan-chain scan-dff

Updated Jul 19, 2026
Verilog

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