skywater130

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Silicon as a Distributed System: Closing the Cross-Layer Loop from Spatial Manufacturing Defects to Wafer-Level Economics

32KB 4-Way Set-Associative L1 Cache Controller with Non-Blocking MSHR, Tree-PLRU, and AXI4 Refills targeting SkyWater 130nm.

asic systemverilog yosys axi4 cache-controller l1-cache mshr pseudo-lru skywater130

Universal Edge AI ASIC: Open-Source Silicon Accelerator for LLMs (llama.cpp GGUF Q4_K/IQ) & Diffusion DiT (Flux, SDXL) in SkyWater SKY130 130nm CMOS.

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