Skip to content

Add post-routing teardrops and saved path width interpolation - #4162

Draft
seveibar wants to merge 5 commits into
mainfrom
feat/saved-route-width-interpolation
Draft

seveibar wants to merge 5 commits into
mainfrom
feat/saved-route-width-interpolation

Conversation

@seveibar

@seveibar seveibar commented Sep 26, 2026 •

Copy link
Copy Markdown
Contributor

Saved pcbTracePaths can describe a tapered wire by assigning different widths to consecutive points and setting width_interpolation_mode: "linear" | "quadratic" on the first point. This converts that input into Circuit JSON's outgoing start_width/end_width fields for both fanout/breakout and autorouting-phase routes.

pcbTracePaths={[
  {
    connection: "U1.1",
    route: [
      { route_type: "wire", x: 0, y: 0, width: 0.8, layer: "top", width_interpolation_mode: "quadratic" },
      { route_type: "wire", x: 1, y: 0, width: 0.2, layer: "top" },
      { route_type: "wire", x: 3, y: 0, width: 0.2, layer: "top" },
    ],
  },
]}

Ordinary segments retain constant-width behavior. Via contact wires use adjacent saved widths instead of reusing the route's first width. Route reversal moves taper metadata to the opposite endpoint and swaps widths, preserving the copper geometry. Raises the SVG dev dependency to the released renderer version with taper support for the visual regression test. README unchanged.

Header-to-0603 saved paths with matching reversed geometry

Automatic teardrops after routing

Trace-level pcbTeardrops, pcbTeardropStart, and pcbTeardropEnd now generate geometry in a new PcbTraceTeardropRender phase after PcbRouteNetIslands and before copper pours. It waits for routing work and does not change the autorouter. Explicit endpoint flags override the trace-wide flag; start/end follow logical from/to even when the stored route is reversed.

The phase adds tapered wire segments at supported centered pad contacts and both sides of vias, retaining the routed centerline and explicit saved-path tapers. Repeated runs restore their original geometry before recomputing, including after copper-pour annotations clone the route. It conservatively skips unsupported pad shapes and segments too short for a taper.

Core passes original Circuit JSON directly to pour and DRC consumers. Native copper-pour support is implemented in tscircuit/copper-pour-solver#104; core must adopt its published release before this draft is ready. Native DRC taper support remains outstanding and is also a release prerequisite. There is no core-side clearance-envelope conversion.

RC filter with a FROM teardrop and reversed storage order

Populated two-layer signal path with via teardrops

Dependency: tscircuit/props#869 supplies the input schema. This PR is a draft until that change is published and core's props dependency/override can be updated. The currently published parser strips the new field. The same pending props release supplies the automatic teardrop controls.

Validation:

  • 14 focused tests pass, including existing saved-route transforms, via endpoints, validation and autorouting phases, plus taper conversion/reversal and visual regression.
  • TypeScript and build pass.
  • Local end-to-end checks with the pending props build passed for fanout and autorouting-phase saved tapers. The published dependency was restored afterward; no local dependency overrides are committed.

Additional validation for the automatic phase: 11 focused regression tests (61 assertions), TypeScript, and build pass. Tests cover endpoint overrides, reversed routes, via layers, repeated rendering, explicit taper preservation, saved routes, and existing copper-pour behavior. End-to-end smoke checks with the pending props build passed with the default autorouter enabled; the published dependency was restored afterward.

Visual fixtures use actual 0603 passives and 2.54 mm headers: an RC filter for endpoint overrides, a populated two-layer signal path for via teardrops, and two header-to-resistor channels for saved interpolation/reversal. All three SVG snapshots were rasterized and visually inspected for pad connections, route crossings, and visible taper geometry.

PCB note-layer arrows identify every expected taper in the visual snapshots. Automatic pad/via examples use longer approaches so the taper is visible beyond the pad; production geometry is unchanged. Verified installed circuit-to-svg 0.0.433 matches the latest published version.

After removing the envelope helper and its test, four focused core tests pass (automatic teardrops and existing copper-pour regression cases).

@vercel

vercel Bot commented Sep 26, 2026 •

Copy link
Copy Markdown

The latest updates on your projects. Learn more about Vercel for GitHub.

Project Deployment Actions Updated
tscircuit-core-benchmarks Ready Ready Preview Sep 26, 2026 7:41pm UTC

Request Review

@seveibar seveibar changed the title Support width interpolation in saved PCB trace paths Add post-routing teardrops and saved path width interpolation Sep 26, 2026

This branch was successfully deployed

1 active deployment
Preview — 7b3b2bc6 Deployed Sep 26, 2026 by vercel[bot]
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant