Skip to content
View venkatalakshmilanda's full-sized avatar
  • India

Block or report venkatalakshmilanda

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. Verilog-HDL Verilog-HDL Public

    A collection of Verilog HDL designs, testbenches, and simulation waveforms for Digital VLSI and RTL Design practice.

    Verilog

  2. parameterized-alu-verilog parameterized-alu-verilog Public

    Parameterized ALU in Verilog HDL with comprehensive testbench and waveform verification.

    Verilog

  3. parameterized_register_file parameterized_register_file Public

    A parameterized Verilog Register File featuring synchronous write, dual asynchronous read ports, configurable data width and memory depth, along with a comprehensive testbench for functional verifi…

    Verilog

  4. student-performance-analytics student-performance-analytics Public

    Analyzes student exam performance across demographics using SQL (joins, aggregations, ranking) and Python (MySQL connector, Matplotlib) to uncover trends in test preparation, parental education, an…

    Python