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Split out of the brightness branch. - BOM corrected against the netlist: JP1 is the PAM8302 header, not a rotary encoder; R1/R2/R3 are series resistors, not pull-ups; the dial is not a board part. Real part numbers for the switches and encoder, plus LCSC equivalents for PCBWay assembly. - Switch boss holes moved to the 2.3 mm the TS32 drawing calls for, and turned into NPTH pads inside the footprint so they are drilled rather than milled. - C1 gains SMD lands overlapping its through-holes, and is typed SMD. - Records why the dial pull-ups were tried and reverted.
Wells's edit in KiCad. Replaces the 1X05_ROUND_70 placeholder with Connector_PinSocket_2.54mm:PinSocket_1x05_P2.54mm_Vertical and moves it to 139, 98.82, matching the female socket the BOM specifies for the PAM8302.
The pour still had the shape of the old 1X05_ROUND_70 pads, leaving three of the socket's pins 0.197 mm from copper where the rules want 0.25. Refilling clears all three; the remaining DRC output is the same baseline the board had before.
…ling - SW1/SW2: hand-made TS32 land -> real maclock:SW_Push_5x7.8x3.8mm_SMD, same placement; value TS32-7-35-BK-160-RA-SMT-TR - ENC1: fake 'Dial' copper -> real E8E8-3.2C60-9B34 encoder footprint, pads netted (ENC_A/ENC_B/GND) - C1: hybrid disc/chip land now SMD-classed with a 1206 chip 3D model (100nF) - J1/J2: JST ZH 2-pin/4-pin vertical connectors (wiring in progress) - C2/C3: 10uF + 100nF decoupling at the PAM8302 Vin (JP1) - README BOM updated; new maclock.pretty footprint library
- ENC1: F-Switch E8E8-3.2C60-9B34 (not on LCSC) -> HOAUC HYCW03-2.8D-5P-S (C55218995); new footprint, bore placed 8.8mm from the left edge / 4mm from the bottom to keep the dial aligned with the case - Nets: split the series-resistor button nets (BTN1/SW1, BTN2/SW2) so each is fully connected; assigned ENC1 pad nets; normalized all board nets to the /-prefixed hierarchical form to match the schematic - Rebuilt maclock-breakout.kicad_sch from the PCB (was a PiInput-only stub): all 11 parts with correct footprints/values/LCSC, custom ENC1 symbol in maclock.kicad_sym; ERC 0/0, board<->schematic parity clean but for benign symbol metadata - BOM: every part now resolves to an LCSC number (added J1 C158011, J2 C157997); PCBWAY_REPLY.md answers the quote's four flagged parts - Switches: added TS24CA and TSB001 side-switch footprints as LCSC-stocked alternatives to the Same Sky TS32; board left on the TS32 for hand-positioning - scripts/: reproducible pcbnew edits (bundled Python) for each board change - README: BOM, sourcing, J1 power switch / J2 power input, schematic status
…k, project lib tables, C1 1206 model
- J1/J2/JP1/PiInput Value -> B2B-ZR(LF)(SN) / B4B-ZR(LF)(SN) / 2.54-1*5PFemale / PZ254V-11-07P on board and schematic (PCBway reads the board's Value column) - /5V and /5V_IN tracks 0.5 -> 1.0 mm; the J2 pad-1 skirt is 0.8 mm and the diagonal out of JP1 pin 2 stays 0.5 mm (2.54 mm socket pitch); long y=98 run restarted at x=141 with a stub so its round end clears JP1 pin 1 (GND) - DRC 0 errors / 0 unconnected; ERC 0; scripts/mpn_values_and_wide_5v.py
- U1 PAM8302AASCR (C113367) on the bottom side where the JP1 socket was; JP1 removed - Input: A+ -> C2 220n -> R4 47k -> IN+; IN- via R5 47k + C3 220n to GND (gain ~9 dB) - C4 1u + C5 10u decoupling, fed by via from the F.Cu 5V trunk; new 5V via at the old JP1 pin-2 spot keeps the F.Cu/B.Cu 5V runs joined - SD pulled up by R6 100k; also brought out on a new PiInput pin 8 (MUTE) along the top edge, so the header is now 1x8 (C492407) - J3 JST ZH 2P speaker connector (C158011), + / - silk, pad 1 = SPK+ - Schematic: new parts + nets, PWR_FLAGs on 5V/GND; ERC 0/0. DRC 0 errors, 0 unconnected, parity only benign field/NC notes. scripts/add_onboard_amp.py rebuilds it from 5ece6d9 - Docs: PCB README BOM + amp section, PCBway reply, build-guide wiring table, root README
- All passives are SMD now; the hybrid THT/SMD land and its library footprint are gone - C1 sits vertically at (143.925, 92.96) on B.Cu, A+ on top toward R3, GND below to the pour - scripts/c1_plain_0603.py replays it from 5d96fa9; ERC 0, DRC 0 errors / 0 unconnected - README BOM, sourcing table and PCBway reply updated; the 'chip or disc' section removed
pinctrl on the running Maclock shows the Waveshare DPI overlay owns GPIO 0-9, 12-17, 20-25 and 10/11/18/19/26/27 are the dial, backlight, audio and buttons, so no header GPIO can drive the amp's shutdown pin. R6 keeps it high (amp always on); the top-edge SD run, pad 8 and the MUTE silk are removed. scripts/revert_mute_pin.py replays it from 1f01ab1. ERC 0, DRC 0/0.
… ring 0.25 mm Hand layout pass: the amp, its passives and the R3/C1 filter now sit in a tight grid at x 127-137 next to the Pi header, U1 inputs facing the passives and outputs facing J3 at (137.75, 101.25). All pad-to-net assignments unchanged. The 5V trunk via was 1.0/0.73 (0.135 mm ring, under PCBway's 0.15 mm); now 1.0/0.5. DRC 0 errors / 0 unconnected.
PCBWAY_REPLY.md answered one specific quote; every part number it carried is in the README BOM. The .rpt files are KiCad check output and are now gitignored.
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…own plugs The stock Maclock power and switch harnesses end in 1.0 mm blade-style plugs (JST SH), not the 1.5 mm ZH the board carried. Swap J1 -> BM02B-SRSS-TB (C160388) and J2 -> BM04B-SRSS-TB (C160390), both top-entry SMD on B.Cu at the same spots on the bottom edge, pad 1 still nearest J1, pads facing the edge and the MP tabs toward the board. Re-routed the two nets the swap disturbed: 5V drops from the y=98 trunk between J1's tabs into pad 1; 5V_IN leaves J1 pad 2, runs west at y=101.9 (above SW2's locator holes, which sit in the edge lane), and drops to the edge lane only west of x=152.5 to reach J2 pad 4. J2's +/- silk moved under its pads. ERC 0, DRC 0 errors / 0 unconnected (the two pre-existing warnings remain). J3 (speaker) stays ZH for now.
Hobby 8 ohm 1 W speakers (Adafruit, Pimoroni, SparkFun) ship with a JST PH 2.0 mm plug, so J3 moves from ZH 1.5 mm to B2B-PH-K-S (C131337). For speakers with bare leads, the new project footprint maclock:JST_PH_B2B-PH-K_1x02_P2.00mm_Vertical_SolderPads adds two 2.54 mm through-hole pads (1.7 mm ring, 1.0 mm hole) beside the housing that duplicate pin 1 (+) and pin 2 (-). Keeping them inside the one footprint means one BOM line and no dummy part to mark DNP. Pin 1 stays at (137.75, 101.25); the SPK- leg now ends on the PH pin 2 at x=135.75 and continues along the board edge to the far solder pad. +/- silk added over the pads. ERC 0, DRC 0 errors / 0 unconnected (same two pre-existing warnings). Speaker spec in the READMEs: 8 ohm, 1 W, 28-40 mm, PH plug or bare leads.
…edge The Maclock's harness plugs need the open (contact-window) side of the SH receptacle facing down, toward the board edge. Both J1 and J2 rotate 180 in place: solder tails now face the board, MP tabs face the edge, pin 1 moves to the end away from J1. Re-routed the supply: 5V drops from the y=98 trunk straight into J1 pin 1; 5V_IN leaves J1 pin 2 eastward, rounds J1's east tab via the edge lane, climbs between SW2's locator holes and J1's west tab to the y=101.9 lane, and reaches J2 pin 4 up J2's east side. J2's +/- silk moved above pins 4/3. DRC 0 errors / 0 unconnected, same two pre-existing warnings.
…placed Hand layout in the PCB editor: J3 becomes the SMD JST PH B2B-PH-SM4-TB (C160352) standing between the amp and the Speaker silk, the two bare-lead solder pads and their project footprint are dropped, J1/J2 sit with their solder tails toward the board edge (intentional), and the 5V / 5V_IN runs are redrawn at 0.6 mm. Fixes on top of that: a GND stitching via at (128.32, 94.03) landed 0.1 mm from the ENC_A track and shorted the dial's A line to ground, so it is removed (seventeen other stitching vias remain, 0 unconnected). The schematic's J3 value, footprint and LCSC fields now match the board. READMEs updated: J3 row, speaker row, all-SMD assembly note. ERC 0, DRC 0 errors / 0 unconnected, parity clean apart from the usual NC-pin notes.
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WIP — ordering boards to test before merging.
What's here
HYCW03-2.8D-5P-S(LCSC-stocked) on a matchingmaclockfootprint, bore positioned to the case dial hole.TSB001A3518A(LCSC-stocked) on the TSB001 land; pinout metered: switch across 1–2, bracket legs 3–4 tied to GND.BM02B/BM04B-SRSS-TB) so the Maclock's own switch and power plugs go straight in. J2 pin mapping verified against the stock harness;+/-on silk.fp-lib-table/sym-lib-tablecommitted. ERC 0. DRC 0 errors, 0 unconnected.maclock-pcb/README.mdwith LCSC numbers for every line and DigiKey numbers (exact or named drop-in) for everything DigiKey carries. The encoder and switches are LCSC-only.Known and accepted
Test plan
Ordering boards to validate: encoder and switch fit against the case, stock plug fit in J1/J2, audio hiss at the new gain.