PhD Candidate in Electrical Engineering at Penn State
Ex-Micron ML Engineer Intern (Pathfinding & Strategy) · Ex-Intel Graduate Technical Intern (Thin Film & AI Process Models)
Building memory-centric AI architectures, Compute-in-Memory accelerators, and open-source MCP tooling for autonomous hardware & ML-systems agents.

Pathfinding and Strategy Group · Richardson, TX (May 2026 – July 2026)

• CIM-NVM Pathfinding for LLM Inference: Analyzed modern LLM workloads (Llama-3, Gemma-3, Gemma-4) and CNNs on Non-Volatile Memory (NVM) Compute-in-Memory (CIM) architectures, quantifying energy, latency, and area trade-offs for next-generation AI accelerators.
• LLM Serving Disaggregation: Characterized hyperscale serving metrics (TPOT, TTFT) under Prefill–Decode (PD) and Attention–FFN (AFD) disaggregation schemes.
• Device Modeling & Error Mitigation: Modeled technology-agnostic NVM characteristics; developed quantization error and CIM analog noise mitigation techniques to preserve model accuracy under limited ADC precision.

Process Technology & Integration · Hillsboro, OR (May 2025 – July 2025)

• Advanced Thin Film Development: Designed and executed exploratory Design of Experiments (DOE) for advanced technology node development.
• Material Characterization: Performed high-resolution material characterization using DSIMS, XRR, stress analysis, and TEM imaging.
• AI-Driven Process Modeling: Developed predictive machine learning frameworks assessing the impact of deposition variations on circuit electrical parameters and device reliability.

My research bridges biological neural mechanisms, emerging non-volatile devices (FeFET, spintronics), and memory-centric ML hardware acceleration:

• TrilinearCIM (arXiv 2604.07628): A novel Double-Gate FeFET (DG-FeFET) CIM architecture executing complete Transformer attention ($Y = A \times B \times C$) in-memory without runtime ferroelectric reprogramming, slashing global buffer requirements by $3\times$.
• RMAAT (ICLR 2026): Recurrent Memory Augmented Astromorphic Transformers, integrating astrocyte-inspired memory compression and replay for efficient long-context processing.
• Energy-Aware Spike Budgeting (NCE 2026): Framework for continual learning in Spiking Neural Networks (SNNs) for neuromorphic vision.
• Bayesian CIM Optimization (EPEPS 2026): Multi-objective Bayesian optimization framework co-optimizing crossbar-based CIM accelerators for DNN inference.

A production-grade, open-source stack built on the open Model Context Protocol (MCP). It enables modern AI coding agents (Cursor, Windsurf, GitHub Copilot / OpenAI Codex, Claude Code, Google Antigravity, OpenCode) to design, verify, synthesize, and lay out silicon in closed-loop workflows.

┌─────────────────────────────────────────────────────────────────────────────┐
│ 1. COGNITIVE LAYER (hw-agent-skills)                                        │
│    Agent applies rtl-reviewer, testbench-writer, and synthesis rubrics.     │
└──────────────────────────────────────┬──────────────────────────────────────┘
                                       │ generates Verilog + self-checking testbench
                                       ▼
┌─────────────────────────────────────────────────────────────────────────────┐
│ 2. PROTOCOL & LINT LAYER (mcp-verilog & mcp-rtl-review)                     │
│    AST-backed semantic review (0–100 score) + iverilog/Verilator simulation.│
└──────────────────────────────────────┬──────────────────────────────────────┘
                                       │ synthesizes netlist
                                       ▼
┌─────────────────────────────────────────────────────────────────────────────┐
│ 3. SYNTHESIS & TIMING LAYER (mcp-yosys & mcp-openroad)                      │
│    Yosys gate synthesis + OpenROAD P&R, floorplanning, placement, and STA.  │
└─────────────────────────────────────────────────────────────────────────────┘

Repository	What It Does	Tech Stack	Status
agentic-asic	Autonomous silicon compilation & signoff orchestrator powered by EDA MCP servers	Python CLI · MCP Client
hw-agent-tooling	Family landing page, 10-gate standard, and landscape analysis	Markdown · Shell
mcp-openroad	OpenROAD physical design, floorplanning, placement, routing & STA	TypeScript · MCP
mcp-rtl-review	AST-backed static RTL review, latch detection & code scoring	TypeScript · Verilator
mcp-yosys	Yosys RTL synthesis, gate cell counting & latch triage	TypeScript · Yosys
mcp-verilog	Verilog/SystemVerilog linting, compilation & simulation	TypeScript · iVerilog
mcp-cocotb	Python-based Cocotb co-simulation testbench runner	TypeScript · Python
hw-agent-skills	Portable agent skills and auto-exported Cursor .mdc rules	YAML · Markdown
eda-docker-images	Rootless Docker / Podman container foundations for open EDA	Dockerfile · Podman
eda-devcontainer	1-click DevContainer profiles for VS Code & Cursor	Dev Containers

High-performance GPU kernel engineering connecting raw CUDA C++ and OpenAI Triton with the Roofline Performance Model.

_{Maintained by @zesun33 · Website: zesun33.github.io · Contact: zesun.ahmed@psu.edu}