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Integrate modern x86 SIMD memory benchmarks alongside the existing SSE2 code. On x86-64 the benchmark now reports SSE2, AVX2 and AVX512 results side by side in a single run. Each tier is gated at runtime on the CPU's actual capabilities (read from /proc/cpuinfo flags via the existing check_cpu_feature()), so CPUs without AVX2/AVX512 keep running only the SSE2 list and never execute an unsupported instruction. The AVX2/AVX512 assembly and benchmark definitions are the work of Joel Luth, based on Siarhei Siamashka's original SSE2 code, with gcc feature-detection help from Tony Mason, taken from the x86 AVX branch hosted by Travis Downs. Original copyright headers are preserved and a Credits section is added to the README. Backends are 64-bit only (guarded on __amd64__) and compile to empty objects on other targets, so non-x86 builds are unaffected. Verified on an Intel Xeon Gold 6338N (Ice Lake-SP): copies are bit-exact, no SIGILL, and the nontemporal-copy path scales SSE2 6.2 -> AVX2 8.8 -> AVX512 11.9 GB/s as expected. Co-authored-by: Joel Luth <joelluth@gmail.com> Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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What
Adds modern x86 SIMD backends (AVX2 and AVX512) alongside the existing SSE2 code. On x86-64 the benchmark now reports SSE2, AVX2 and AVX512 side by side in a single run, gated at runtime on the CPU's actual capabilities (read from
/proc/cpuinfoflags via the existingcheck_cpu_feature()), so older CPUs keep running only the SSE2 list and never execute an unsupported instruction.Provenance / credits
This is not new code — it gathers existing community work and wires it into this fork:
letrout/jluth) — author of the AVX2/AVX512 assembly + benchmarks, originally proposed upstream as ssvb/tinymembench#23, based on Siarhei Siamashka's (ssvb) original SSE2 code.fsgeek) — gcc AVX512 feature-detection help.Original copyright headers are preserved in
x86-avx2.{S,h}/x86-avx512.{S,h}, a Credits section is added to the README, and the commit carriesCo-authored-by: Joel Luth.Design
x86-avx2.{S,h},x86-avx512.{S,h}.asm-opt.cdynamically concatenates SSE2 → AVX2 → AVX512 lists based on detected features; all AVX code is guarded on__amd64__and compiles to empty objects on other targets, so non-x86 builds are unaffected.size_t sizeparams were aligned tointto match thebench_infofunction-pointer signature used by SSE2.Verification (Intel Xeon Gold 6338N, Ice Lake-SP)
gcc -ccompiles both backends; a standalone harness confirms every copy is bit-exact and noSIGILL.tinymembenchbinary lists all three tiers, runs to completion (exit 0), full latency section included.Note on scope
A survey of the fork ecosystem found the remaining community patches to be either already present in this fork's nuumio base (ARM/portability fixes — confirmed by empty cherry-picks) or not mergeable as-is (e.g. an arter97 hugetlbfs change that
exit(1)s without preconfigured huge pages). AVX2/AVX512 is the one substantial, clean, non-redundant increment — hence this focused PR.