[Fix] Hold DMA AXI address valid until ready

[flaviens]

Description

Issue AXI read and write addresses without waiting for READY. Waiting first can deadlock against a conforming target; each VALID now remains asserted until its handshake.

Collateral (docs, reports, design examples, case IDs):

None.

• Document Update Required? No

Tests added:

Directed external RTL regression with READY asserted three cycles after VALID.

Tests run:

Verilator end-to-end DMA engine test: source read through the data FIFO to one destination write.

[Copilot]

Pull request overview

Adjusts the DMA AXI address-channel handshake behavior to avoid potential deadlock with conforming AXI targets by asserting address VALID independent of READY and holding it until the handshake completes.

Changes:

• Write engine: stop waiting for AWREADY before issuing a write address request; assert AWVALID in SEND_WR_REQ until AWREADY handshakes.
• Read engine: stop waiting for ARREADY before asserting ARVALID; remain in SEND_RD_REQ until ARREADY handshakes before advancing.

Reviewed changes

Copilot reviewed 2 out of 2 changed files in this pull request and generated no comments.

File	Description
tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv	Removes AWREADY gating in IDLE and asserts AWVALID unconditionally in the request state until handshake.
tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_read_engine.sv	Removes ARREADY gating prior to request, and holds in request state until ARREADY completes the handshake.

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