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[Fix] Hold DMA AXI address valid until ready #33

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[Fix] Hold DMA AXI address valid until ready #33

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5 changes: 3 additions & 2 deletions tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_read_engine.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -91,13 +91,14 @@ module dma_read_engine #(
end

state[ADDR_SETUP_BIT]:
if (src_mem.arready & ((rd_req_cnt-rlast_cnt)<NUM_PENDING_RDS))
if ((rd_req_cnt-rlast_cnt)<NUM_PENDING_RDS)
next = SEND_RD_REQ;
else
next = ADDR_SETUP;

state[SEND_RD_REQ_BIT]:
if ((rd_req_cnt+1) < num_rd_reqs) next = ADDR_SETUP;
if (!src_mem.arready) next = SEND_RD_REQ;
else if ((rd_req_cnt+1) < num_rd_reqs) next = ADDR_SETUP;
else if ((rd_req_cnt+1) >= num_rd_reqs) next = CP_RSP_TO_FIFO;
else next = SEND_RD_REQ;

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4 changes: 2 additions & 2 deletions tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,7 @@ module dma_write_engine #(
next = XXX;
unique case (1'b1)
state[IDLE_BIT]: begin
if (descriptor.descriptor_control.go & descriptor_fifo_not_empty & dest_mem.awready & rd_fifo_if.not_empty)next = SEND_WR_REQ;
if (descriptor.descriptor_control.go & descriptor_fifo_not_empty & rd_fifo_if.not_empty) next = SEND_WR_REQ;
else next = IDLE;
end

Expand Down Expand Up @@ -275,7 +275,7 @@ module dma_write_engine #(
end

state[SEND_WR_REQ_BIT]:begin
dest_mem.awvalid = dest_mem.awready;
dest_mem.awvalid = 1'b1;
rd_fifo_if.rd_en = 1'b0;
dest_mem_wvalid = 1'b0;
end
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