dbSta: Fix zero slew and net delay issue in `dmp_ceff_two_pole` and `dmp_ceff_lambert_w` delay calculators by jhkim-pii · Pull Request #11229 · The-OpenROAD-Project/OpenROAD

jhkim-pii · 2026-08-25T05:45:29Z

Summary

Fixes placement RC reduction for dmp_ceff_two_pole and dmp_ceff_lambert_w delay calculators.

Problem

dmp_ceff_two_pole and dmp_ceff_lambert_w wrongly calculate wire load slew and delay while dmp_ceff_elmore calculates it correctly.

bazel test //src/dbSta/test:dmp_ceff_dcalc_load_propagation-tcl_test --test_output=all --nocache_test_results

  === Default (dmp_ceff_elmore) ===
  Startpoint: in (input port)
  Endpoint: out (output port)
  Path Group: unconstrained
  Path Type: max

  Fanout         Cap        Slew       Delay        Time   Description
  ---------------------------------------------------------------------------------------------
                                    0.000000    0.000000 ^ input external delay
       1    8.546090    0.000000    0.000000    0.000000 ^ in (in)
                                                           in (net)
                        0.001452    0.001188    0.001188 ^ u1/A (BUF_X1)
       2   12.446165    0.029541    0.043706    0.044894 ^ u1/Z (BUF_X1)
                                                           n1 (net)
                        0.029703    0.003075    0.047969 ^ u2/A (BUF_X1)
       1    7.534790    0.019359    0.041592    0.089562 ^ u2/Z (BUF_X1)
                                                           out (net)
                        0.019370    0.001344    0.090906 ^ out (out)
                                                0.090906   data arrival time
  ---------------------------------------------------------------------------------------------
  (Path is unconstrained)



  === TwoPole (dmp_ceff_two_pole) ===
  Startpoint: in (input port)
  Endpoint: out (output port)
  Path Group: unconstrained
  Path Type: max

  Fanout         Cap        Slew       Delay        Time   Description
  ---------------------------------------------------------------------------------------------
                                    0.000000    0.000000 ^ input external delay
       1    8.546090    0.000000    0.000000    0.000000 ^ in (in)
                                                           in (net)
                        0.000000    0.000000    0.000000 ^ u1/A (BUF_X1)
       2   12.446165    0.029540    0.043105    0.043105 ^ u1/Z (BUF_X1)
                                                           n1 (net)
                        0.029540    0.000000    0.043105 ^ u2/A (BUF_X1)
       1    7.534790    0.019358    0.041559    0.084664 ^ u2/Z (BUF_X1)
                                                           out (net)
                        0.019358    0.000000    0.084664 ^ out (out)
                                                0.084664   data arrival time
  ---------------------------------------------------------------------------------------------
  (Path is unconstrained)



  === Lambert-W (dmp_ceff_lambert_w) ===
  Startpoint: in (input port)
  Endpoint: out (output port)
  Path Group: unconstrained
  Path Type: max

  Fanout         Cap        Slew       Delay        Time   Description
  ---------------------------------------------------------------------------------------------
                                    0.000000    0.000000 ^ input external delay
       1    8.546090    0.000000    0.000000    0.000000 ^ in (in)
                                                           in (net)
                        0.000000    0.000000    0.000000 ^ u1/A (BUF_X1)
       2   12.446165    0.026673    0.039863    0.039863 ^ u1/Z (BUF_X1)
                                                           n1 (net)
                        0.026673    0.000000    0.039863 ^ u2/A (BUF_X1)
       1    7.534790    0.020074    0.041402    0.081265 ^ u2/Z (BUF_X1)
                                                           out (net)
                        0.020074    0.000000    0.081265 ^ out (out)
                                                0.081265   data arrival time
  ---------------------------------------------------------------------------------------------
  (Path is unconstrained)


  Error: dmp_ceff_dcalc_load_propagation.tcl, 101 DMP Ceff load propagation failed:
    - TwoPole: u1/A load slew is zero
    - TwoPole: in -> u1/A net delay is zero
    - TwoPole: u1/Z -> u2/A net delay is zero
    - TwoPole: u2/A load slew equals u1/Z driver slew
    - Lambert-W: u1/A load slew is zero
    - Lambert-W: in -> u1/A net delay is zero
    - Lambert-W: u1/Z -> u2/A net delay is zero
    - Lambert-W: u2/A load slew equals u1/Z driver slew

Cause

estimate_parasitics -placement reduces RC according to delay calculator model.
dmp_ceff_two_pole and dmp_ceff_lambert_w require PiPoleResidue2 parasitic data while dmp_ceff_elmore model requires PiElmore parasitic data.
However, the reduceParasitic(..., Pin*, ...) API of dmp_ceff_two_pole and dmp_ceff_lambert_w generates PiElmore parasitic data instead of PiPoleResidue2 because the reduceParasitic() API overriding is missing in DmpCeffTwoPoleDelayCalc implementation.
If PiElmore parasitic data is wrongly fed into dmp_ceff_two_pole or dmp_ceff_lambert_w delay calculator, wire delay and slew calculation logic is skipped and the following initial values are returned.

  double wire_delay = 0.0;                // MAKE WIRE DELAY 0
  double load_slew = in_slew;           // LOAD SLEW = DRIVER SLEW

Solution

Override DmpCeffTwoPoleDelayCalc::reduceParasitic() in OpenSTA so the reduction calls reduceToPiPoleResidue2() instead of inheriting PiElmore reduction.
Mirrors the restored virtual hook in dbSta so Lambert-W inherits the corrected TwoPole reduction path.

bazel test //src/dbSta/test:dmp_ceff_dcalc_load_propagation-tcl_test --test_output=all --nocache_test_results

  === Default (dmp_ceff_elmore) ===
  Startpoint: in (input port)
  Endpoint: out (output port)
  Path Group: unconstrained
  Path Type: max

  Fanout         Cap        Slew       Delay        Time   Description
  ---------------------------------------------------------------------------------------------
                                    0.000000    0.000000 ^ input external delay
       1    8.546090    0.000000    0.000000    0.000000 ^ in (in)
                                                           in (net)
                        0.001452    0.001188    0.001188 ^ u1/A (BUF_X1)
       2   12.446165    0.029541    0.043706    0.044894 ^ u1/Z (BUF_X1)
                                                           n1 (net)
                        0.029703    0.003075    0.047969 ^ u2/A (BUF_X1)
       1    7.534790    0.019359    0.041592    0.089562 ^ u2/Z (BUF_X1)
                                                           out (net)
                        0.019370    0.001344    0.090906 ^ out (out)
                                                0.090906   data arrival time
  ---------------------------------------------------------------------------------------------
  (Path is unconstrained)



  === TwoPole (dmp_ceff_two_pole) ===
  Startpoint: in (input port)
  Endpoint: out (output port)
  Path Group: unconstrained
  Path Type: max

  Fanout         Cap        Slew       Delay        Time   Description
  ---------------------------------------------------------------------------------------------
                                    0.000000    0.000000 ^ input external delay
       1    8.546090    0.000000    0.000000    0.000000 ^ in (in)
                                                           in (net)
                        0.001452    0.001188    0.001188 ^ u1/A (BUF_X1)
       2   12.446165    0.029541    0.043706    0.044894 ^ u1/Z (BUF_X1)
                                                           n1 (net)
                        0.029542    0.003100    0.047994 ^ u2/A (BUF_X1)
       1    7.534790    0.019358    0.041560    0.089554 ^ u2/Z (BUF_X1)
                                                           out (net)
                        0.019358    0.001350    0.090903 ^ out (out)
                                                0.090903   data arrival time
  ---------------------------------------------------------------------------------------------
  (Path is unconstrained)



  === Lambert-W (dmp_ceff_lambert_w) ===
  Startpoint: in (input port)
  Endpoint: out (output port)
  Path Group: unconstrained
  Path Type: max

  Fanout         Cap        Slew       Delay        Time   Description
  ---------------------------------------------------------------------------------------------
                                    0.000000    0.000000 ^ input external delay
       1    8.546090    0.000000    0.000000    0.000000 ^ in (in)
                                                           in (net)
                        0.001452    0.001188    0.001188 ^ u1/A (BUF_X1)
       2   12.446165    0.026984    0.040794    0.041982 ^ u1/Z (BUF_X1)
                                                           n1 (net)
                        0.026986    0.003099    0.045082 ^ u2/A (BUF_X1)
       1    7.534790    0.020076    0.041465    0.086547 ^ u2/Z (BUF_X1)
                                                           out (net)
                        0.020076    0.001350    0.087897 ^ out (out)
                                                0.087897   data arrival time
  ---------------------------------------------------------------------------------------------
  (Path is unconstrained)


  pass

Required OpenSTA fix

https://github.com/The-OpenROAD-Project-private/OpenSTA/pull/86

Add a minimal two-buffer Tcl regression registered in CMake and Bazel. Demonstrate that Lambert-W reports zero input slew and zero PiElmore net delays while the default calculator propagates both. Compare report_checks output for the two calculators and fail with exact timing object names. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

Apply tclfmt 0.7.0 formatting to the multiline Elmore guard so the Tcl lint workflow leaves the source tree unchanged. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

gemini-code-assist

Code Review

This pull request adds a new integration test, dmp_ceff_lambert_w_pi_elmore, to verify that the Lambert-W delay calculator correctly propagates nonzero slew and delay for PiElmore parasitics. The test is integrated into both the CMake and Bazel build systems. Feedback on the changes suggests simplifying the ternary expressions in the Bazel configuration to direct boolean expressions to make the Starlark code more idiomatic and readable.

Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com> Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

Rename the regression around its placement-load propagation contract instead of the Lambert-W implementation. Add TwoPole report_checks output and object-level assertions so the red test captures the shared PiElmore propagation defect in both TwoPole and Lambert-W. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

Update OpenSTA to the TwoPole PiPoleResidue2 reduction fix and mirror the restored virtual hook for Lambert-W. Re-estimate placement parasitics per calculator and use a branched net so the regression verifies positive delay and receiver-specific slew. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

Advance the OpenSTA submodule to include the direct regression that verifies dmp_ceff_two_pole eager reduction returns PiPoleResidue. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

jhkim-pii added 2 commits August 25, 2026 14:21

test: Format Lambert-W regression Tcl

a22a4e3

Apply tclfmt 0.7.0 formatting to the multiline Elmore guard so the Tcl lint workflow leaves the source tree unchanged. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

jhkim-pii self-assigned this Aug 25, 2026

github-actions Bot added the size/M label Aug 25, 2026

gemini-code-assist Bot reviewed Aug 25, 2026

View reviewed changes

Comment thread src/dbSta/test/BUILD Outdated

jhkim-pii and others added 2 commits August 25, 2026 14:50

Update src/dbSta/test/BUILD

f05dc69

Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com> Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

jhkim-pii changed the title ~~dbSta: Add Lambert-W zero slew and net delay regression~~ dbSta: Add DMP Ceff load propagation regression Aug 25, 2026

jhkim-pii changed the title ~~dbSta: Add DMP Ceff load propagation regression~~ (DO NOT MERGE) dbSta: Add DMP Ceff load propagation regression Aug 25, 2026

jhkim-pii mentioned this pull request Aug 26, 2026

dcalc: Restore TwoPole parasitic reduction The-OpenROAD-Project/OpenSTA#406

Closed

jhkim-pii added 2 commits August 26, 2026 09:36

sta: Update TwoPole reduction regression

3882341

Advance the OpenSTA submodule to include the direct regression that verifies dmp_ceff_two_pole eager reduction returns PiPoleResidue. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

jhkim-pii changed the title ~~(DO NOT MERGE) dbSta: Add DMP Ceff load propagation regression~~ (DO NOT MERGE) dbSta: Fix zero slew and net delay issue in dmp_ceff_two_pole and dmp_ceff_lambert_w delay calculators Aug 26, 2026

jhkim-pii changed the title ~~(DO NOT MERGE) dbSta: Fix zero slew and net delay issue in dmp_ceff_two_pole and dmp_ceff_lambert_w delay calculators~~ dbSta: Fix zero slew and net delay issue in dmp_ceff_two_pole and dmp_ceff_lambert_w delay calculators Aug 26, 2026

jhkim-pii marked this pull request as ready for review August 26, 2026 05:45

jhkim-pii requested review from a team as code owners August 26, 2026 05:45

jhkim-pii requested a review from maliberty August 26, 2026 05:45

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dbSta: Fix zero slew and net delay issue in `dmp_ceff_two_pole` and `dmp_ceff_lambert_w` delay calculators - #11229

dbSta: Fix zero slew and net delay issue in `dmp_ceff_two_pole` and `dmp_ceff_lambert_w` delay calculators#11229
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The-OpenROAD-Project-staging:secure-lambertw-zero-net-delay

jhkim-pii commented Aug 25, 2026 •

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Summary

Problem

Cause

Solution

Required OpenSTA fix

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jhkim-pii commented Aug 25, 2026 •

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