clk: qcom: gcc-shikra: Add additional frequencies for EMAC RGMII clocks - #911
clk: qcom: gcc-shikra: Add additional frequencies for EMAC RGMII clocks #911imrashai wants to merge 2 commits into
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…RGMII clocks Add support for 2.5MHz and 25MHz GCC EMAC RGMII clock frequencies required for EMAC 10M and 100M speeds respectively on Qualcomm Shikra SoC. Tested-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260722-b4-shikra-gcc-emac-freqs-v2-1-2e480e2de8de@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
CLK_ALPHA_PLL_TYPE_DEFAULT_EVO type PLLs do not have the PLL_TEST_CTL_U1 register, so clk_alpha_pll_configure() does not program test_ctl_hi1_val for this PLL type. The GCC PLL configurations for QCM2290, Shikra and SM6115 wrongly use test_ctl_hi1_val instead of test_ctl_hi_val, deviating from the hardware recommended settings. Fix them to use test_ctl_hi_val. Fixes: 496d1a1 ("clk: qcom: Add Global Clock Controller driver for QCM2290") Fixes: 01cf3e2 ("clk: qcom: Add Global clock controller support on Qualcomm Shikra SoC") Fixes: e88c533 ("clk: qcom: gcc-sm6115: Add missing PLL config properties") Cc: stable@vger.kernel.org Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260729-pll-test-ctrl-fixup-v1-1-246d79589380@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Merge Check Failed: CR Not Eligible for Merge CR 4635794 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
PR #911 — validate-patchPR: #911
Final Summary
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PR #911 — checker-log-analyzerPR: #911
Detailed report: Full report
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Add support for 2.5MHz and 25MHz GCC EMAC RGMII clock frequencies required for EMAC 10M and 100M speeds respectively on Qualcomm Shikra SoC.
Alos, add the test_ctl_hi field fix-up for DEFAULT_EVO PLLs.
CRs-Fixed: 4635794