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clk: qcom: gcc-shikra: Add additional frequencies for EMAC RGMII clocks #911

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clk: qcom: gcc-shikra: Add additional frequencies for EMAC RGMII clocks #911

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23a966c
UPSTREAM: clk: qcom: gcc-shikra: Add additional frequencies for EMAC …
imrashai Jul 22, 2026
f143ebd
UPSTREAM: clk: qcom: Fix test_ctl_hi field for DEFAULT_EVO PLLs
imrashai Jul 29, 2026
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6 changes: 3 additions & 3 deletions drivers/clk/qcom/gcc-qcm2290.c
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Original file line number Diff line number Diff line change
Expand Up @@ -116,7 +116,7 @@ static const struct alpha_pll_config gpll10_config = {
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055B,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
};

static struct clk_alpha_pll gpll10 = {
Expand Down Expand Up @@ -148,7 +148,7 @@ static const struct alpha_pll_config gpll11_config = {
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055B,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
};

static struct clk_alpha_pll gpll11 = {
Expand Down Expand Up @@ -309,7 +309,7 @@ static const struct alpha_pll_config gpll8_config = {
.post_div_val = 0x1 << 8,
.post_div_mask = GENMASK(11, 8),
.config_ctl_val = 0x4001055B,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
};

static struct clk_alpha_pll gpll8 = {
Expand Down
8 changes: 5 additions & 3 deletions drivers/clk/qcom/gcc-shikra.c
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Original file line number Diff line number Diff line change
Expand Up @@ -123,7 +123,7 @@ static const struct alpha_pll_config gpll10_config = {
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
};

static struct clk_alpha_pll gpll10 = {
Expand Down Expand Up @@ -156,7 +156,7 @@ static const struct alpha_pll_config gpll11_config = {
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
};

static struct clk_alpha_pll gpll11 = {
Expand Down Expand Up @@ -361,7 +361,7 @@ static const struct alpha_pll_config gpll8_config = {
.post_div_val = BIT(8),
.post_div_mask = GENMASK(11, 8),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
};

static struct clk_alpha_pll gpll8 = {
Expand Down Expand Up @@ -1244,6 +1244,8 @@ static struct clk_rcg2 gcc_emac0_ptp_clk_src = {
};

static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = {
F(2500000, P_GPLL0_OUT_AUX2, 10, 1, 12),
F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
F(125000000, P_GPLL12_OUT_AUX2, 4, 0, 0),
F(250000000, P_GPLL12_OUT_EARLY, 4, 0, 0),
Expand Down
6 changes: 3 additions & 3 deletions drivers/clk/qcom/gcc-sm6115.c
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Original file line number Diff line number Diff line change
Expand Up @@ -120,7 +120,7 @@ static const struct alpha_pll_config gpll10_config = {
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
.test_ctl_hi_mask = 0x1,
};

Expand Down Expand Up @@ -173,7 +173,7 @@ static const struct alpha_pll_config gpll11_config = {
.vco_val = 0x2 << 20,
.vco_mask = GENMASK(21, 20),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
.test_ctl_hi_mask = 0x1,
};

Expand Down Expand Up @@ -367,7 +367,7 @@ static const struct alpha_pll_config gpll8_config = {
.post_div_val = 0x1 << 8,
.post_div_mask = GENMASK(11, 8),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
.test_ctl_hi_mask = 0x1,
};

Expand Down