CDSP and adreno smmu changes - #916
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Add a dedicated binding for the Qualcomm Nord SoC PAS devices: ADSP and CDSPs. Nord ADSP uses CX and MX power domains while the CDSPs add an NSP domain on top of that. Nord ADSP was previously documented in qcom,sm8550-pas.yaml, which hardcodes a two-entry power-domains list and therefore cannot express the third NSP domain the CDSPs require. Drop the Nord bits from that binding so Nord is described in exactly one place. This supersedes commit a602117 ("FROMLIST: dt-bindings: remoteproc: qcom,sm8550-pas: Document Nord ADSP"). Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260729023508.879752-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
Add support for the 4 CDSPs found on Nord SoC. Each CDSP uses the CX, MX and NSP power domains, and is cold booted by Linux, so no early_boot flag is needed unlike the Nord ADSP. The device tree nodes for these already exist in nord.dtsi, with the power domains and XO clock supplied from nord-embedded.dtsi, but the driver had no matching resource descriptors, so the CDSP nodes did not probe. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260729023508.879752-4-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
Add the Adreno GPU SMMMUs (MMU-500) for both GPU instances and the PCIe SMMU (SMMUv3) nodes. Wire up the gpucc clock and power domain on both adreno SMMU nodes in nord-embedded.dtsi for embedded Nord variants where gpucc is available. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
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Adding adreno smmu in nord DT.
Adding support for CDSP 0 -3 in remoteproc dt and drivers.