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CDSP and adreno smmu changes #916

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fb5db73
FROMLIST: dt-bindings: remoteproc: qcom,nord-pas: Document Nord PAS
Aug 6, 2026
45e2321
FROMLIST: remoteproc: qcom: pas: Add Nord CDSP support
Aug 6, 2026
61d0d26
PENDING: arm64: dts: qcom: nord: Add adreno and PCIe SMMU nodes
bibekpatro Aug 6, 2026
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173 changes: 173 additions & 0 deletions Documentation/devicetree/bindings/remoteproc/qcom,nord-pas.yaml
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@@ -0,0 +1,173 @@
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/qcom,nord-pas.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Nord SoC Peripheral Authentication Service

maintainers:
- Shawn Guo <shengchao.guo@oss.qualcomm.com>

description:
Qualcomm Nord SoC Peripheral Authentication Service loads and boots firmware
on the Qualcomm DSP Hexagon cores.

properties:
compatible:
enum:
- qcom,nord-adsp-pas
- qcom,nord-cdsp0-pas
- qcom,nord-cdsp1-pas
- qcom,nord-cdsp2-pas
- qcom,nord-cdsp3-pas

power-domains:
minItems: 2
items:
- description: CX power domain
- description: MX power domain
- description: NSP power domain

power-domain-names:
minItems: 2
items:
- const: cx
- const: mx
- const: nsp

reg:
maxItems: 1

clocks:
items:
- description: XO clock

clock-names:
items:
- const: xo

qcom,qmp:
$ref: /schemas/types.yaml#/definitions/phandle
description: Reference to the AOSS side-channel message RAM.

smd-edge: false

firmware-name:
items:
- description: Firmware name of the Hexagon core
- description: Firmware name of the Hexagon Devicetree

memory-region:
items:
- description: Memory region for main Firmware authentication
- description: Memory region for Devicetree Firmware authentication

interrupts:
items:
- description: Watchdog interrupt
- description: Fatal interrupt
- description: Ready interrupt
- description: Handover interrupt
- description: Stop acknowledge interrupt
- description: Shutdown acknowledge interrupt

interrupt-names:
items:
- const: wdog
- const: fatal
- const: ready
- const: handover
- const: stop-ack
- const: shutdown-ack

qcom,smem-states:
maxItems: 1
description: States used by the AP to signal the Hexagon core

qcom,smem-state-names:
maxItems: 1
description: The names of the state bits used for SMP2P output

required:
- compatible
- reg
- memory-region

allOf:
- $ref: /schemas/remoteproc/qcom,pas-common.yaml#
- if:
properties:
compatible:
enum:
- qcom,nord-adsp-pas
then:
properties:
power-domains:
maxItems: 2
power-domain-names:
maxItems: 2
else:
properties:
power-domains:
minItems: 3
power-domain-names:
minItems: 3

unevaluatedProperties: false

examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#define IPCC_MPROC_ADSP0

remoteproc@4c00000 {
compatible = "qcom,nord-adsp-pas";
reg = <0x04c00000 0x10000>;

clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";

interrupts-extended = <&intc GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack",
"shutdown-ack";

memory-region = <&hpass_dsp0_mem>, <&hpass_dsp0_dtb_mem>;

firmware-name = "qcom/nord/adsp.mbn",
"qcom/nord/adsp_dtb.mbn";

power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MX>;
power-domain-names = "cx",
"mx";

qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";

glink-edge {
interrupts-extended = <&ipcc IPCC_MPROC_ADSP0
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_MPROC_ADSP0 IPCC_MPROC_SIGNAL_GLINK_QMP>;

label = "adsp";
qcom,remote-pid = <2>;

/* ... */
};
};
19 changes: 0 additions & 19 deletions Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
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Expand Up @@ -17,7 +17,6 @@ properties:
compatible:
oneOf:
- enum:
- qcom,nord-adsp-pas
- qcom,sdx75-mpss-pas
- qcom,sm8550-adsp-pas
- qcom,sm8550-cdsp-pas
Expand Down Expand Up @@ -141,7 +140,6 @@ allOf:
- qcom,kaanapali-cdsp-pas
- qcom,maili-adsp-pas
- qcom,maili-cdsp-pas
- qcom,nord-adsp-pas
- qcom,sm8750-adsp-pas
then:
properties:
Expand Down Expand Up @@ -246,23 +244,6 @@ allOf:
- const: lcx
- const: lmx

- if:
properties:
compatible:
contains:
enum:
- qcom,nord-adsp-pas
then:
properties:
power-domains:
items:
- description: CX power domain
- description: MX power domain
power-domain-names:
items:
- const: cx
- const: mx

- if:
properties:
compatible:
Expand Down
12 changes: 12 additions & 0 deletions arch/arm64/boot/dts/qcom/nord-embedded.dtsi
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Expand Up @@ -2228,3 +2228,15 @@
maximum-speed = "high-speed";
qcom,select-utmi-as-pipe-clk;
};

&adreno_smmu_0 {
clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>;
clock-names = "hlos";
power-domains = <&gpucc GPU_CC_CX_GDSC>;
};

&adreno_smmu_1 {
clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>;
clock-names = "hlos";
power-domains = <&gpucc GPU_CC_CX_GDSC>;
};
95 changes: 95 additions & 0 deletions arch/arm64/boot/dts/qcom/nord.dtsi
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Expand Up @@ -2323,6 +2323,101 @@
<GIC_ESPI 319 IRQ_TYPE_LEVEL_HIGH>;
};

adreno_smmu_0: iommu@3da0000 {
compatible = "qcom,nord-smmu-500", "qcom,adreno-smmu",
"qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x03da0000 0x0 0x40000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};

adreno_smmu_1: iommu@98a0000 {
compatible = "qcom,nord-smmu-500", "qcom,adreno-smmu",
"qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x098a0000 0x0 0x40000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 963 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 889 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 960 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 961 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 964 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 965 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 966 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 967 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 968 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 969 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 970 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 971 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 972 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 973 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 974 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
};

pcie_smmu: iommu@9980000 {
compatible = "arm,smmu-v3";
reg = <0x0 0x09980000 0x0 0x20000>;
interrupts = <GIC_SPI 930 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 932 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 934 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq",
"cmdq-sync",
"gerror";
dma-coherent;
#iommu-cells = <1>;
};

intc: interrupt-controller@17000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x17000000 0x0 0x10000>,
Expand Down
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